Signed-off-by: Peng Hao <peng.hao2@xxxxxxxxxx>
---
.../devicetree/bindings/arm/pvpanic-mmio.txt | 29 ++++++++++++++++++++++
1 file changed, 29 insertions(+)
create mode 100644 Documentation/devicetree/bindings/arm/pvpanic-mmio.txt
diff --git a/Documentation/devicetree/bindings/arm/pvpanic-mmio.txt b/Documentation/devicetree/bindings/arm/pvpanic-mmio.txt
new file mode 100644
index 0000000..a6bdacd
--- /dev/null
+++ b/Documentation/devicetree/bindings/arm/pvpanic-mmio.txt
@@ -0,0 +1,29 @@
+* QEMU PVPANIC MMIO Configuration bindings for ARM
+
+QEMU's emulation / virtualization targets provide the following PVPANIC
+MMIO Configuration interface on the "virt" machine.
+type:
+
+- a read-write, 16-bit wide data register.
+
+QEMU exposes the data register to guests as memory mapped registers.
+
+Required properties:
+
+- compatible: "qemu,pvpanic-mmio".
+- reg: the MMIO region used by the device.
+ * Bytes 0x0 Write panic event to the reg when guest OS panics.
+ * Bytes 0x1 Reserved.
+
+Example:
+
+/ {
+ #size-cells = <0x2>;
+ #address-cells = <0x2>;
+
+ pvpanic-mmio@9060000 {
+ compatible = "qemu,pvpanic-mmio";
+ reg = <0x0 0x9060000 0x0 0x2>;
+ };
+};
+
--
1.8.3.1
