On Tue, Nov 28, 2017 at 11:24:07PM +0200, Jarkko Sakkinen wrote: > On Tue, Nov 28, 2017 at 10:53:24PM +0200, Jarkko Sakkinen wrote: > > > So, maybe something like this? > > > > > > After SGX is activated[1] the IA32_SGXLEPUBKEYHASHn MSRs are writable > > > if and only if SGX_LC is set in the IA32_FEATURE_CONTROL MSR and the > > > IA32_FEATURE_CONTROL MSR is locked, otherwise they are read-only. > > > > > > For example, firmware can allow the OS to change the launch enclave > > > root key by setting IA32_FEATURE_CONTROL.SGX_LC, and thus give the > > > OS complete control over the enclaves it runs. Alternatively, > > > firmware can clear IA32_FEATURE_CONTROL.SGX_LC to lock down the root > > > key and restrict the OS to running enclaves signed with the root key > > > or whitelisted/trusted by a launch enclave (which must be signed with > > > the root key). > > > > > > [1] SGX related bits in IA32_FEATURE_CONTROL cannot be set until SGX > > > is activated, e.g. by firmware. SGX activation is triggered by > > > setting bit 0 in MSR 0x7a. Until SGX is activated, the LE hash > > > MSRs are writable, e.g. to allow firmware to lock down the LE > > > root key with a non-Intel value. > > > > Thanks I'll use this as a basis and move most of the crappy commit > > message to the commit (with some editing) that defines the MSRs. > > Not sure after all if I'm following this. > > IA32_FEATURE_CONTROL[17] contols whether the MSRs are writable or not > after the feature control MSR is locked. SGX_LC means just that the > CPU supports the launch configuration. > > /Jarkko I used this commit message with some minor editing in the commit that defines the MSRs and squashed commits that define cpuid level 7 bits. Can you peer check the commit messages? They are in the le branch. /Jarkko
