On Mon, 2017-07-10 at 20:23 +0200, Carlo Caione wrote: > On Mon, Jul 10, 2017 at 7:50 PM, Carlo Caione <carlo@xxxxxxxxxxxx> > wrote: > > On Mon, Jul 10, 2017 at 6:06 PM, Darren Hart <dvhart@xxxxxxxxxxxxx> > > wrote: > > > On Mon, Jul 10, 2017 at 05:20:43PM +0300, Andy Shevchenko wrote: > > > > On Mon, 2017-07-10 at 16:15 +0200, Carlo Caione wrote: >>>>> The best solution would probably be avoiding to gate the clocks at >>>>> all > > > > > when booting if these are being already used by the firmware, > > > > > but IIUC > > > > > this information is not always available in the enable clock > > > > > register. > > > In those two cases, are we able to determine programmatically if > > > the > > > clock is already in use by the firmware? (via the enabled register > > > I > > > presume?) > I checked again the enable registers in plt_clk_register() and I can > actually see that the pmc_plt_clk_4 is already enabled at boot by the > firmware. So yeah, at least in my case we are able to determine > programmatically if the clock is used already by the firmware. So, then it should be trivial to update the PMC clock driver to follow firmware settings. Please, Cc Enric when send the patch / new mail regarding topic. Thanks, for investigating this! -- Andy Shevchenko <andriy.shevchenko@xxxxxxxxxxxxxxx> Intel Finland Oy
