Yes, just applying this patch will fix the existing offset issue. On Sun, Apr 2, 2017 at 7:11 AM, Andy Shevchenko <andy.shevchenko@xxxxxxxxx> wrote: > On Sat, Apr 1, 2017 at 2:27 AM, Kuppuswamy Sathyanarayanan > <sathyanarayanan.kuppuswamy@xxxxxxxxxxxxxxx> wrote: >> According to Broxton APL PMC spec, gcr mem region starts >> at offset 0x1000 from ipc mem base address. In this driver, >> PLAT_RESOURCE_GCR_OFFSET macro defines the offset of GCR >> memory region from IPC mem region. So we should use 0x1000(4K) >> as GCR offset. But currently this driver uses 0x1008 as GCT >> offset.This patch fixes this issue. > > > So, if I apply this one independently, would it fix an existin issue? > >> >> Signed-off-by: Kuppuswamy Sathyanarayanan <sathyanarayanan.kuppuswamy@xxxxxxxxxxxxxxx> >> --- >> drivers/platform/x86/intel_pmc_ipc.c | 2 +- >> 1 file changed, 1 insertion(+), 1 deletion(-) >> >> Changes since v3: >> * Updated the commit history >> >> diff --git a/drivers/platform/x86/intel_pmc_ipc.c b/drivers/platform/x86/intel_pmc_ipc.c >> index 0651d47..0a33592 100644 >> --- a/drivers/platform/x86/intel_pmc_ipc.c >> +++ b/drivers/platform/x86/intel_pmc_ipc.c >> @@ -82,7 +82,7 @@ >> /* exported resources from IFWI */ >> #define PLAT_RESOURCE_IPC_INDEX 0 >> #define PLAT_RESOURCE_IPC_SIZE 0x1000 >> -#define PLAT_RESOURCE_GCR_OFFSET 0x1008 >> +#define PLAT_RESOURCE_GCR_OFFSET 0x1000 >> #define PLAT_RESOURCE_GCR_SIZE 0x1000 >> #define PLAT_RESOURCE_BIOS_DATA_INDEX 1 >> #define PLAT_RESOURCE_BIOS_IFACE_INDEX 2 >> -- >> 2.7.4 >> > > > > -- > With Best Regards, > Andy Shevchenko -- -- Sathya
