On 2018-01-10 01:31:58 +0100, Andreas Joseph Krogh wrote: > På onsdag 10. januar 2018 kl. 01:01:26, skrev Andres Freund <andres@xxxxxxxxxxx > <mailto:andres@xxxxxxxxxxx>>: > On 2018-01-10 00:25:08 +0100, Andreas Joseph Krogh wrote: > > But SIMD-instructions are also HW-accellerated by modern CPUs IIUC? > > Sure. Still measurable, but even if weren't, it's irrelevant given my > primary point: > > > The checksum computations have some impact, but if there's bigger impact > > it's much more likely to be related to the fact that some hint bit > > writes to a page now needs to be WAL logged. > > which isn't mitigated by SIMD / hardware CRC / whatnot. > > Aha, so enabling CRC causes hint-bits to be written causing extra WAL-logging, > which woudn't be the case without CRC enabled? > Thanks for pointing that out. Well, enabling checksums enables that. CRCs don't play a role for data checksums. CRCs are a specific class of checksums, a specific one of those is used in our WAL logging, but the data checksum algorithm isn't in that class. Greetings, Andres Freund
