Signed-off-by: Akira Yokosawa <akiyks@xxxxxxxxx> --- appendix/whymb/whymemorybarriers.tex | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/appendix/whymb/whymemorybarriers.tex b/appendix/whymb/whymemorybarriers.tex index 01c6a703..57800c10 100644 --- a/appendix/whymb/whymemorybarriers.tex +++ b/appendix/whymb/whymemorybarriers.tex @@ -611,7 +611,7 @@ are up to date (``V'') or not (``I''). Initially, the CPU cache lines in which the data would reside are in the ``invalid'' state, and the data is valid in memory, as shown in step~0. -In step~1, CPU~0 loads the data at address~0, incuring a cache miss, +In step~1, CPU~0 loads the data at address~0, incurring a cache miss, loading the value into its cache, and transitioning that cache line to the ``shared'' state. The contents of memory at address~0 remain valid. @@ -664,7 +664,7 @@ However, because its cache holds that data in the ``modified'' state, CPU~2 can immediately execute that atomic increment without any change to cache or memory state. -In step~8.1, CPU~1 loads loads the data at address~0, incuring a cache +In step~8.1, CPU~1 loads the data at address~0, incurring a cache miss. Because the data from address~8 is modified in its cache, it must first flush that data to memory, transitioning its cache line to -- 2.34.1
