Linux kernel's commit 598056d5af8f ("[POWERPC] Fix rmb to order
cacheable vs. noncacheable") [1] strengthened rmb() to use the sync
instruction and a later commit 957ab07b44d8 ("powerpc: Optimise
smp_rmb") [2] updated the comment block above, both back in 2008.
Currently, Section 15.5.6 mentions that lwsync is good enough for
rmb(). This text has been there since the first commit of perfbook
made in August 2008, without ever being updated since.
Reflect the current state of affairs in the text.
Also consistently use "primitive" for kernel APIs.
This discrepancy was caught while reviewing a patch submission at
lkml [3].
Link: [1] https://git.kernel.org/linus/598056d5af8f
Link: [2] https://git.kernel.org/linus/957ab07b44d8
Link: [3] https://lore.kernel.org/r/20230222090344.189270-1-kconsul@xxxxxxxxxxxxxxxxxx/
Signed-off-by: Akira Yokosawa <akiyks@xxxxxxxxx>
---
memorder/memorder.tex | 18 ++++++++++--------
1 file changed, 10 insertions(+), 8 deletions(-)
diff --git a/memorder/memorder.tex b/memorder/memorder.tex
index ee8119125c23..d158d4f348cf 100644
--- a/memorder/memorder.tex
+++ b/memorder/memorder.tex
@@ -4982,20 +4982,22 @@ instructions~\cite{PowerPC94,MichaelLyons05a}:
\end{description}
Unfortunately, none of these instructions line up exactly with Linux's
-{\tt wmb()} primitive, which requires {\em all} stores to be ordered,
-but does not require the other high-overhead actions of the {\tt sync}
+\co{wmb()} primitive, which requires \emph{all} stores to be ordered,
+but does not require the other high-overhead actions of the \co{sync}
instruction.
+The \co{rmb()} primitive doesn't have a matching light-weight instruction
+either.
But there is no choice:
-{ppc64} versions of {\tt wmb()} and {\tt mb()} are defined to be the
-heavyweight {\tt sync} instruction.
-However, Linux's \co{smp_wmb()} instruction is never used for MMIO
+{ppc64} versions of \co{wmb()}, \co{rmb()}, and \co{mb()} are defined
+to be the heavyweight \co{sync} instruction.
+However, Linux's \co{smp_wmb()} primitive is never used for MMIO
(since a driver must carefully order MMIOs in UP as well as
SMP kernels, after all), so it is defined to be the lighter weight
\co{eieio} or \co{lwsync} instruction~\cite{PaulEMcKenney2016LinuxKernelMMIO}.
This instruction may well be unique in having a five-vowel mnemonic.
-The \co{smp_mb()} instruction is also defined to be the {\tt sync}
-instruction, but both \co{smp_rmb()} and \co{rmb()} are defined to
-be the lighter-weight {\tt lwsync} instruction.
+The \co{smp_mb()} primitive is also defined to be the \co{sync}
+instruction, while \co{smp_rmb()} is defined to be the lighter-weight
+\co{lwsync} instruction.
\Power{} features ``cumulativity'', which can be used to obtain
transitivity.
--
2.25.1
