This commit adds missing unbreakable spaces in 'cpu/'.
Signed-off-by: SeongJae Park <sj38.park@xxxxxxxxx>
---
cpu/overheads.tex | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/cpu/overheads.tex b/cpu/overheads.tex
index 28462d49..2cfe931b 100644
--- a/cpu/overheads.tex
+++ b/cpu/overheads.tex
@@ -48,21 +48,21 @@ events might ensue:
\begin{enumerate}
\item CPU~0 checks its local cache, and does not find the cacheline.
It therefore records the write in its store buffer.
-\item A request for this cacheline is forwarded to CPU~0's and 1's
+\item A request for this cacheline is forwarded to CPU~0's and~1's
interconnect, which checks CPU~1's local cache, and does not
find the cacheline.
\item This request is forwarded to the system interconnect, which
checks with the other three dies, learning that the cacheline
- is held by the die containing CPU~6 and 7.
-\item This request is forwarded to CPU~6's and 7's interconnect, which
+ is held by the die containing CPU~6 and~7.
+\item This request is forwarded to CPU~6's and~7's interconnect, which
checks both CPUs' caches, finding the value in CPU~7's cache.
\item CPU~7 forwards the cacheline to its interconnect, and also
flushes the cacheline from its cache.
-\item CPU~6's and 7's interconnect forwards the cacheline to the
+\item CPU~6's and~7's interconnect forwards the cacheline to the
system interconnect.
-\item The system interconnect forwards the cacheline to CPU~0's and 1's
+\item The system interconnect forwards the cacheline to CPU~0's and~1's
interconnect.
-\item CPU~0's and 1's interconnect forwards the cacheline to CPU~0's
+\item CPU~0's and~1's interconnect forwards the cacheline to CPU~0's
cache.
\item CPU~0 can now complete the write, updating the relevant portions
of the newly arrived cacheline from the value previously
@@ -106,7 +106,7 @@ events might ensue:
Why is it necessary to flush the cacheline from CPU~7's cache?
}\QuickQuizAnswerE{
If the cacheline was not flushed from CPU~7's cache, then
- CPUs~0 and 7 might have different values for the same set
+ CPUs~0 and~7 might have different values for the same set
of variables in the cacheline.
This sort of incoherence greatly complicates parallel software,
which is why so wise hardware architects avoid it.
@@ -358,7 +358,7 @@ thousand clock cycles.
threads.
Smaller systems often achieve better latency, as may be seen in
\cref{tab:cpu:Performance of Synchronization Mechanisms on 16-CPU 2.8GHz Intel X5550 (Nehalem) System},
- which represents a much smaller system with only 16 hardware threads.
+ which represents a much smaller system with only 16~hardware threads.
A similar view is provided by the rows of
\cref{tab:cpu:CPU 0 View of Synchronization Mechanisms on 8-Socket System With Intel Xeon Platinum 8176 CPUs at 2.10GHz}
down to and including the two ``Off-core'' rows.
--
2.17.1
