On Mon, Nov 23, 2020 at 01:06:21PM -0800, Paul E. McKenney wrote:
> On Mon, Nov 23, 2020 at 12:14:05AM +0900, Akira Yokosawa wrote:
> > Hi Paul,
> >
> > So this *not-pull* request is to show you my WIP branch to add indices
> > to perfbook.
And this time with the promised patch.
Thanx, Paul
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diff --git a/glossary.tex b/glossary.tex
index 386946e..8270945 100644
--- a/glossary.tex
+++ b/glossary.tex
@@ -153,7 +153,7 @@
\item[Direct-Mapped Cache:]\index{Direct-mapped cache}
A cache with only one way, so that it may hold only one cache
line with a given hash value.
-\item[Embarrassingly Parallel:]\index{Embarrassingly parellel}
+\item[Embarrassingly Parallel:]\index{Embarrassingly parallel}
A problem or algorithm where adding threads does not significantly
increase the overall cost of the computation, resulting in
linear speedups as threads are added (assuming sufficient
@@ -248,7 +248,7 @@
used so heavily that there is often a CPU waiting on it.
Reducing lock contention is often a concern when designing
parallel algorithms and when implementing parallel programs.
-\item[Memory Consistency:]\index{Memory consisitency}
+\item[Memory Consistency:]\index{Memory consistency}
A set of properties that impose constraints on the order in
which accesses to groups of variables appear to occur.
Memory consistency models range from sequential consistency,
@@ -382,7 +382,7 @@
as well as its cache so as to ensure that the software sees
the memory operations performed by this CPU as if they
were carried out in program order.
-\item[Superscalar CPU:]\index{Superscaler CPU}
+\item[Superscalar CPU:]\index{Superscalar CPU}
A scalar (non-vector) CPU capable of executing multiple instructions
concurrently.
This is a step up from a pipelined CPU that executes multiple
