Hello,
I have a question about the following scenario (considering POWER arch):
initial { x = 0; y = 0; }
thread0 {
x = 1;
--
lwsync;
y = 1;
}
thread1 {
a = y;
isync;
b = x;
}
Because "isync" is not a memory barrier this example doesn't have read/write barrier pairing. However, if I understand correctly, lwsync will ensure that "x = 1" will become visible to thread1 before lwsync is done and before "y = 1" will become visible. So "isync" here can be sort of control dependency as it ensures that "a = y" will be performed before "b = x" and even will flush the pipeline according to POWER9 spec.
Can someone comment on this scenario and tell if I am right or where I am wrong.
С Уважением, Поляков Артем Юрьевич
Best regards, Artem Y. Polyakov
Best regards, Artem Y. Polyakov
