>From 0cd6e0e44f5cc4be1b1a71caa04e2e9321b24c94 Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@xxxxxxxxx>
Date: Sun, 5 Nov 2017 22:19:06 +0900
Subject: [PATCH 3/4] appendix/whymb: Fix layout in answers to quick quizzes
Signed-off-by: Akira Yokosawa <akiyks@xxxxxxxxx>
---
appendix/whymb/whymemorybarriers.tex | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/appendix/whymb/whymemorybarriers.tex b/appendix/whymb/whymemorybarriers.tex
index efd67c9..256b9af 100644
--- a/appendix/whymb/whymemorybarriers.tex
+++ b/appendix/whymb/whymemorybarriers.tex
@@ -377,7 +377,8 @@ levels of the system architecture.
to the shared bus first,
and that CPU ``wins''. The other CPU must invalidate its copy of the
cache line and transmit an ``invalidate acknowledge'' message
- to the other CPU. \\
+ to the other CPU.
+
Of course, the losing CPU can be expected to immediately issue a
``read invalidate'' transaction, so the winning CPU's victory will
be quite ephemeral.
@@ -1525,7 +1526,6 @@ assert(r1 == 0 || a == 1);
No changes are needed to the code in the first two columns,
because interrupt handlers run atomically from the perspective
of the interrupted code.
-
} \QuickQuizEnd
\QuickQuiz{}
--
2.7.4
--
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