>From 0bec999ee614a8c92d42876957b1072329b62829 Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@xxxxxxxxx>
Date: Mon, 23 Oct 2017 23:13:26 +0900
Subject: [PATCH 1/3] whymb: Update table layout
Signed-off-by: Akira Yokosawa <akiyks@xxxxxxxxx>
---
appendix/whymb/whymemorybarriers.tex | 20 ++++++++------------
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/appendix/whymb/whymemorybarriers.tex b/appendix/whymb/whymemorybarriers.tex
index b52c2e5..422948e 100644
--- a/appendix/whymb/whymemorybarriers.tex
+++ b/appendix/whymb/whymemorybarriers.tex
@@ -565,29 +565,25 @@ Finally, CPU~1 reads the cache line at address~8, which uses a
\begin{table*}
\small
\centering
-\begin{tabular}{r|c|l||c|c|c|c||c|c}
- & & & \multicolumn{4}{c||}{CPU Cache} & \multicolumn{2}{c}{Memory} \\
- \cline{4-7}
+\renewcommand*{\arraystretch}{1.2}
+\rowcolors{6}{}{lightgray}
+\begin{tabular}{rclcccccc}
+ \toprule
+ & & & \multicolumn{4}{c}{CPU Cache} & \multicolumn{2}{c}{Memory} \\
+ \cmidrule(lr){4-7} \cmidrule(l){8-9}
Sequence \# & CPU \# & Operation & 0 & 1 & 2 & 3 & 0 & 8 \\
- \hline
+ \cmidrule(r){1-3} \cmidrule(lr){4-7} \cmidrule(l){8-9}
% Seq CPU Operation ------------- CPU ------------- - Memory -
% 0 1 2 3 0 8
- \hline
0 & & Initial State & $-$/I & $-$/I & $-$/I & $-$/I & V & V \\
- \hline
1 & 0 & Load & 0/S & $-$/I & $-$/I & $-$/I & V & V \\
- \hline
2 & 3 & Load & 0/S & $-$/I & $-$/I & 0/S & V & V \\
- \hline
3 & 0 & Invalidation & 8/S & $-$/I & $-$/I & 0/S & V & V \\
- \hline
4 & 2 & RMW & 8/S & $-$/I & 0/E & $-$/I & V & V \\
- \hline
5 & 2 & Store & 8/S & $-$/I & 0/M & $-$/I & I & V \\
- \hline
6 & 1 & Atomic Inc & 8/S & 0/M & $-$/I & $-$/I & I & V \\
- \hline
7 & 1 & Writeback & 8/S & 8/S & $-$/I & $-$/I & V & V \\
+ \bottomrule
\end{tabular}
\caption{Cache Coherence Example}
\label{tab:app:whymb:Cache Coherence Example}
--
2.7.4
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