>From de45acd5a73354cbe03abaf3130177687c77e4cb Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@xxxxxxxxx>
Date: Wed, 12 Jul 2017 23:21:52 +0900
Subject: [PATCH 6/6] advsync: Adjust value expressions in Tables 14.1 and 14.2
As x0 and x1 are pointers, they should be in dereferenced form.
Signed-off-by: Akira Yokosawa <akiyks@xxxxxxxxx>
---
advsync/memorybarriers.tex | 48 +++++++++++++++++++++++-----------------------
1 file changed, 24 insertions(+), 24 deletions(-)
diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
index 8693cac..b9dd1fa 100644
--- a/advsync/memorybarriers.tex
+++ b/advsync/memorybarriers.tex
@@ -179,7 +179,7 @@ Figure~\ref{fig:advsync:Memory Misordering: Store-Buffering Litmus Test}.
\begin{table*}
\small
-\centering\OneColumnHSpace{-.1in}
+\centering\OneColumnHSpace{-.2in}
\begin{tabular}{r||l|l|l||l|l|l}
& \multicolumn{3}{c||}{CPU 0} & \multicolumn{3}{c}{CPU 1} \\
\cline{2-7}
@@ -187,20 +187,20 @@ Figure~\ref{fig:advsync:Memory Misordering: Store-Buffering Litmus Test}.
Instruction & Store Buffer & Cache \\
\hline
\hline
- 1 & (Initial state) & & \tco{x1==0} &
- (Initial state) & & \tco{x0==0} \\
+ 1 & (Initial state) & & \tco{*x1==0} &
+ (Initial state) & & \tco{*x0==0} \\
\hline
- 2 & \tco{*x0 = 2} & \tco{x0==2} & \tco{x1==0} &
- \tco{*x1 = 2;} & \tco{x1==2} & \tco{x0==0} \\
+ 2 & \tco{*x0 = 2;} & \tco{*x0==2} & \tco{*x1==0} &
+ \tco{*x1 = 2;} & \tco{*x1==2} & \tco{*x0==0} \\
\hline
- 3 & \tco{r2 = *x1;} (0) & \tco{x0==2} & \tco{x1==0} &
- \tco{r2 = *x0;} (0) & \tco{x1==2} & \tco{x0==0} \\
+ 3 & \tco{r2 = *x1;} (0) & \tco{*x0==2} & \tco{*x1==0} &
+ \tco{r2 = *x0;} (0) & \tco{*x1==2} & \tco{*x0==0} \\
\hline
- 4 & (Read-invalidate) & \tco{x0==2} & \tco{x0==0} &
- (Read-invalidate) & \tco{x1==2} & \tco{x1==0} \\
+ 4 & (Read-invalidate) & \tco{*x0==2} & \tco{*x0==0} &
+ (Read-invalidate) & \tco{*x1==2} & \tco{*x1==0} \\
\hline
- 5 & (Finish store) & & \tco{x0==2} &
- (Finish store) & & \tco{x1==2} \\
+ 5 & (Finish store) & & \tco{*x0==2} &
+ (Finish store) & & \tco{*x1==2} \\
\end{tabular}
\caption{Memory Misordering: Store-Buffering Sequence of Events}
\label{tab:advsync:Memory Misordering: Store-Buffering Sequence of Events}
@@ -343,7 +343,7 @@ Figure~\ref{fig:advsync:Memory Misordering: Store-Buffering Litmus Test}.
\begin{table*}
\small
-\centering\OneColumnHSpace{-0.75in}
+\centering\OneColumnHSpace{-0.2in}
\begin{tabular}{r||l|l|l||l|l|l}
& \multicolumn{3}{c||}{CPU 0} & \multicolumn{3}{c}{CPU 1} \\
\cline{2-7}
@@ -351,23 +351,23 @@ Figure~\ref{fig:advsync:Memory Misordering: Store-Buffering Litmus Test}.
Instruction & Store Buffer & Cache \\
\hline
\hline
- 1 & (Initial state) & & \tco{x1==0} &
- (Initial state) & & \tco{x0==0} \\
+ 1 & (Initial state) & & \tco{*x1==0} &
+ (Initial state) & & \tco{*x0==0} \\
\hline
- 2 & \tco{*x0 = 2} & \tco{x0==2} & \tco{x1==0} &
- \tco{*x1 = 2;} & \tco{x1==2} & \tco{x0==0} \\
+ 2 & \tco{*x0 = 2;} & \tco{*x0==2} & \tco{*x1==0} &
+ \tco{*x1 = 2;} & \tco{*x1==2} & \tco{*x0==0} \\
\hline
- 3 & \tco{smp_mb()} & \tco{x0==2} & \tco{x1==0} &
- \tco{smp_mb()} & \tco{x1==2} & \tco{x0==0} \\
+ 3 & \tco{smp_mb();} & \tco{*x0==2} & \tco{*x1==0} &
+ \tco{smp_mb();} & \tco{*x1==2} & \tco{*x0==0} \\
\hline
- 4 & (Read-invalidate) & \tco{x0==2} & \tco{x0==0} &
- (Read-invalidate) & \tco{x1==2} & \tco{x1==0} \\
+ 4 & (Read-invalidate) & \tco{*x0==2} & \tco{*x0==0} &
+ (Read-invalidate) & \tco{*x1==2} & \tco{*x1==0} \\
\hline
- 5 & (Finish store) & & \tco{x0==2} &
- (Finish store) & & \tco{x1==2} \\
+ 5 & (Finish store) & & \tco{*x0==2} &
+ (Finish store) & & \tco{*x1==2} \\
\hline
- 6 & \tco{r2 = *x1;} (2) & & \tco{x1==2} &
- \tco{r2 = *x0;} (2) & & \tco{x0==2} \\
+ 6 & \tco{r2 = *x1;} (2) & & \tco{*x1==2} &
+ \tco{r2 = *x0;} (2) & & \tco{*x0==2} \\
\end{tabular}
\caption{Memory Ordering: Store-Buffering Sequence of Events}
\label{tab:advsync:Memory Ordering: Store-Buffering Sequence of Events}
--
2.7.4
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