On Fri, Jun 30, 2017 at 12:20:20AM +0900, Akira Yokosawa wrote:
> >From 309126f6728e3b2b9abf98f77fc97788afb527ea Mon Sep 17 00:00:00 2001
> From: Akira Yokosawa <akiyks@xxxxxxxxx>
> Date: Fri, 30 Jun 2017 00:10:01 +0900
> Subject: [PATCH] advsync: Trivial typo fixes
>
> Signed-off-by: Akira Yokosawa <akiyks@xxxxxxxxx>
Good eyes! Applied and pushed, thank you!
Thanx, Paul
> ---
> advsync/memorybarriers.tex | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
> index dfa7681..03ad184 100644
> --- a/advsync/memorybarriers.tex
> +++ b/advsync/memorybarriers.tex
> @@ -136,7 +136,7 @@ from multiple CPUs to a set of shared variables.
> In cache-coherent systems, if the caches hold multiple copies of a given
> variable, all the copies of that variable must have the same value.
> This works extremely well for concurrent reads, but not so well for
> -concurrent writes: Each write musd do something about all
> +concurrent writes: Each write must do something about all
> copies of the old value (another cache miss!), which, given the finite
> speed of light and the atomic nature of matter, will be slower
> than impatient software hackers would like.
> @@ -163,7 +163,7 @@ of order, which can in turn cause serious confusion, as illustrated in
> Figure~\ref{fig:advsync:CPUs Can Do Things Out of Order}.
> In particular, these store buffers can cause the memory misordering
> shown in the store-buffering litmus test in
> -Figure~\ref{fig:advsync:Memory Misordering: Store-Buffering Litmus Test}
> +Figure~\ref{fig:advsync:Memory Misordering: Store-Buffering Litmus Test}.
>
> % @@@ More here. Some sort of illustration of store-buffering misordering
>
> --
> 2.7.4
>
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