>From 8e91a3c8c27c2d39d7954138676be3e0b2f5cf98 Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiyks@xxxxxxxxx>
Date: Sun, 16 Apr 2017 07:58:21 +0900
Subject: [PATCH 06/14] advsync: Use pseudo asm in another reordering example
Also make it clear the initial values are for shared variables.
Signed-off-by: Akira Yokosawa <akiyks@xxxxxxxxx>
---
advsync/memorybarriers.tex | 9 +++++----
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
index f60eb3a..270c868 100644
--- a/advsync/memorybarriers.tex
+++ b/advsync/memorybarriers.tex
@@ -1209,17 +1209,18 @@ perceived by the loads made by another CPU in the same order as the stores were
committed.
As a further example, consider this sequence of events given the
-initial values {\tt \{A~=~1, B~=~2, C~=~3, P~=~\&A, Q~=~\&C\}}:
+initial values of shared variables
+{\tt \{A~=~1, B~=~2, C~=~3, P~=~\&A, Q~=~\&C\}}:
\vspace{5pt}
\begin{minipage}[t]{\columnwidth}
\tt
\scriptsize
\begin{tabular}{l|l}
- \nf{CPU 1} & \nf{CPU 2} \\
+ \nf{CPU 1} & \nf{CPU 2} \\
\hline
- B = 4; & Q = P; \\
- P = \&B & D = *Q; \\
+ STORE B = 4 & Q = LOAD P \\
+ STORE P = \&B & D = LOAD *Q \\
\end{tabular}
\end{minipage}
\vspace{5pt}
--
2.7.4
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