>From 6503699d2abef5f5774577d7bd86f1a51829525b Mon Sep 17 00:00:00 2001
From: Akira Yokosawa <akiysw@xxxxxxxxx>
Date: Sat, 30 Apr 2016 12:43:57 +0900
Subject: [RFC PATCH] advsync: Replace table with diagrams in "Variables Can
Have More ..."
In commit 8de1474e3282 ("Add larger multiple-value-write scenario"),
a table representing difference in opinions of 15 CPUs of a
shared variable was introduced. However, a diagram similar to
Figure 14.2 is nicer for readers.
This commit replaces the table with a figure which consists of
two diagrams. One shows the overall picture and the other shows
the zoom-up of the beginning period.
It also updates related text appropriately.
It removes the explanation of non-response period added in
commit 12eb7c30e5db ("Explain why cells in table 14.2 can be blank")
since the diagrams ignore such periods just as in Figure 14.2.
It also adds unpolished source code of a conversion program
used to generate .fig files.
It also adds the input file to the conversion program for
other people to see if the extracted data is correct.
Detailed explanation of the format of the input file and the
conversion program is planned to be added in a future commit.
Signed-off-by: Akira Yokosawa <akiysw@xxxxxxxxx>
---
Makefile | 2 +
advsync/MoreThanOneValue-15CPU.eps | 1062 ++++++++++++++++++++++++++++++++++
advsync/MoreThanOneValue-15CPU.fig | 391 +++++++++++++
advsync/MoreThanOneValue-15CPU.input | 16 +
advsync/memorybarriers.tex | 149 +----
utilities/MoreThanOneValue-15CPU.c | 185 ++++++
6 files changed, 1673 insertions(+), 132 deletions(-)
create mode 100644 advsync/MoreThanOneValue-15CPU.eps
create mode 100644 advsync/MoreThanOneValue-15CPU.fig
create mode 100644 advsync/MoreThanOneValue-15CPU.input
create mode 100644 utilities/MoreThanOneValue-15CPU.c
diff --git a/Makefile b/Makefile
index 4d9ed30..1b508b1 100644
--- a/Makefile
+++ b/Makefile
@@ -93,6 +93,8 @@ EPSSOURCES = \
advsync/DataDependencySupplied.eps \
advsync/MemoryArchitecture.eps \
advsync/MemoryBarrierPairing.eps \
+ advsync/MoreThanOneValue.eps \
+ advsync/MoreThanOneValue-15CPU.eps \
advsync/ReadBarrierNeeded.eps \
advsync/ReadBarrierSupplied.eps \
advsync/ReadBarrierSupplied1.eps \
diff --git a/advsync/MoreThanOneValue-15CPU.eps b/advsync/MoreThanOneValue-15CPU.eps
new file mode 100644
index 0000000..91552d4
--- /dev/null
+++ b/advsync/MoreThanOneValue-15CPU.eps
@@ -0,0 +1,1062 @@
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+% here ends figure;
+pagefooter
+showpage
+%%Trailer
+%EOF
+
+%%EndDocument
+ @endspecial Black Black eop end
+%%Trailer
+
+userdict /end-hook known{end-hook}if
+%%EOF
diff --git a/advsync/MoreThanOneValue-15CPU.fig b/advsync/MoreThanOneValue-15CPU.fig
new file mode 100644
index 0000000..fc75e7a
--- /dev/null
+++ b/advsync/MoreThanOneValue-15CPU.fig
@@ -0,0 +1,391 @@
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+4 2 0 50 0 16 9 0.0000 4 135 540 670 3980 CPU 15\001
+-6
+6 90 4860 8235 9315
+2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5
+ 700 4860 2500 4860 2500 5130 700 5130 700 4860
+2 2 0 1 0 4 50 0 20 0.000 0 0 -1 0 0 5
+ 2500 4860 8200 4860 8200 5130 2500 5130 2500 4860
+2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5
+ 700 5130 3100 5130 3100 5400 700 5400 700 5130
+2 2 0 1 0 6 50 0 20 0.000 0 0 -1 0 0 5
+ 3100 5130 8200 5130 8200 5400 3100 5400 3100 5130
+2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5
+ 700 5400 3250 5400 3250 5670 700 5670 700 5400
+2 2 0 1 0 31 50 0 20 0.000 0 0 -1 0 0 5
+ 3250 5400 8200 5400 8200 5670 3250 5670 3250 5400
+2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5
+ 700 5670 2950 5670 2950 5940 700 5940 700 5670
+2 2 0 1 0 14 50 0 20 0.000 0 0 -1 0 0 5
+ 2950 5670 8200 5670 8200 5940 2950 5940 2950 5670
+2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5
+ 700 5940 3100 5940 3100 6210 700 6210 700 5940
+2 2 0 1 0 2 50 0 20 0.000 0 0 -1 0 0 5
+ 3100 5940 8200 5940 8200 6210 3100 6210 3100 5940
+2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5
+ 700 6210 3250 6210 3250 6480 700 6480 700 6210
+2 2 0 1 0 3 50 0 20 0.000 0 0 -1 0 0 5
+ 3250 6210 8200 6210 8200 6480 3250 6480 3250 6210
+2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5
+ 700 6480 3400 6480 3400 6750 700 6750 700 6480
+2 2 0 1 0 16 50 0 20 0.000 0 0 -1 0 0 5
+ 3400 6480 8200 6480 8200 6750 3400 6750 3400 6480
+2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5
+ 700 6750 2950 6750 2950 7020 700 7020 700 6750
+2 2 0 1 0 27 50 0 20 0.000 0 0 -1 0 0 5
+ 2950 6750 4450 6750 4450 7020 2950 7020 2950 6750
+2 2 0 1 0 7 50 0 20 0.000 0 0 -1 0 0 5
+ 4450 6750 8200 6750 8200 7020 4450 7020 4450 6750
+2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5
+ 700 7020 3250 7020 3250 7290 700 7290 700 7020
+2 2 0 1 0 7 50 0 20 0.000 0 0 -1 0 0 5
+ 3250 7020 8200 7020 8200 7290 3250 7290 3250 7020
+2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5
+ 700 7290 3850 7290 3850 7560 700 7560 700 7290
+2 2 0 1 0 5 50 0 20 0.000 0 0 -1 0 0 5
+ 3850 7290 8200 7290 8200 7560 3850 7560 3850 7290
+2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5
+ 700 7560 3700 7560 3700 7830 700 7830 700 7560
+2 2 0 1 0 29 50 0 20 0.000 0 0 -1 0 0 5
+ 3700 7560 8200 7560 8200 7830 3700 7830 3700 7560
+2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5
+ 700 7830 2650 7830 2650 8100 700 8100 700 7830
+2 2 0 1 0 22 50 0 20 0.000 0 0 -1 0 0 5
+ 2650 7830 8200 7830 8200 8100 2650 8100 2650 7830
+2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5
+ 700 8100 2500 8100 2500 8370 700 8370 700 8100
+2 2 0 1 0 20 50 0 20 0.000 0 0 -1 0 0 5
+ 2500 8100 8200 8100 8200 8370 2500 8370 2500 8100
+2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5
+ 700 8370 2650 8370 2650 8640 700 8640 700 8370
+2 2 0 1 0 28 50 0 20 0.000 0 0 -1 0 0 5
+ 2650 8370 3700 8370 3700 8640 2650 8640 2650 8370
+2 2 0 1 0 12 50 0 20 0.000 0 0 -1 0 0 5
+ 3700 8370 8200 8370 8200 8640 3700 8640 3700 8370
+2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5
+ 700 8640 3100 8640 3100 8910 700 8910 700 8640
+2 2 0 1 0 12 50 0 20 0.000 0 0 -1 0 0 5
+ 3100 8640 8200 8640 8200 8910 3100 8910 3100 8640
+2 1 0 2 0 7 50 0 -1 0.000 0 0 -1 1 0 2
+ 1 1 1.00 60.00 120.00
+ 700 9110 8200 9110
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
+ 700 9060 700 9160
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
+ 1450 9060 1450 9160
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
+ 2200 9060 2200 9160
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
+ 2950 9060 2950 9160
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
+ 3700 9060 3700 9160
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
+ 4450 9060 4450 9160
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
+ 5200 9060 5200 9160
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
+ 5950 9060 5950 9160
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
+ 6700 9060 6700 9160
+2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2
+ 7450 9060 7450 9160
+4 1 0 50 0 18 9 0.0000 4 135 90 5350 5060 1\001
+4 1 0 50 0 18 9 0.0000 4 135 90 5650 5330 2\001
+4 1 0 50 0 18 9 0.0000 4 135 90 5650 5600 3\001
+4 1 0 50 0 18 9 0.0000 4 135 90 5500 5870 4\001
+4 1 0 50 0 18 9 0.0000 4 135 90 5650 6140 5\001
+4 1 0 50 0 18 9 0.0000 4 135 90 5650 6410 6\001
+4 1 0 50 0 18 9 0.0000 4 135 90 5800 6680 7\001
+4 1 0 50 0 18 9 0.0000 4 135 90 3700 6950 8\001
+4 1 0 50 0 18 9 0.0000 4 135 90 6250 6950 9\001
+4 1 0 50 0 18 9 0.0000 4 135 90 5650 7220 9\001
+4 1 0 50 0 18 9 0.0000 4 135 180 5950 7490 10\001
+4 1 0 50 0 18 9 0.0000 4 135 180 5950 7760 11\001
+4 1 0 50 0 18 9 0.0000 4 135 180 5350 8030 12\001
+4 1 0 50 0 18 9 0.0000 4 135 180 5350 8300 13\001
+4 1 0 50 0 18 9 0.0000 4 135 180 3100 8570 14\001
+4 1 0 50 0 18 9 0.0000 4 135 180 5950 8570 15\001
+4 1 0 50 0 18 9 0.0000 4 135 180 5650 8840 15\001
+4 1 0 50 0 16 9 0.0000 4 135 90 700 9310 0\001
+4 1 0 50 0 16 9 0.0000 4 135 90 1450 9310 5\001
+4 1 0 50 0 16 9 0.0000 4 135 180 2200 9310 10\001
+4 1 0 50 0 16 9 0.0000 4 135 180 2950 9310 15\001
+4 1 0 50 0 16 9 0.0000 4 135 180 3700 9310 20\001
+4 1 0 50 0 16 9 0.0000 4 135 180 4450 9310 25\001
+4 1 0 50 0 16 9 0.0000 4 135 180 5200 9310 30\001
+4 1 0 50 0 16 9 0.0000 4 135 180 5950 9310 35\001
+4 1 0 50 0 16 9 0.0000 4 135 180 6700 9310 40\001
+4 1 0 50 0 16 9 0.0000 4 135 180 7450 9310 45\001
+4 2 0 50 0 16 9 0.0000 4 135 540 670 5060 CPU 1\001
+4 2 0 50 0 16 9 0.0000 4 135 540 670 5330 CPU 2\001
+4 2 0 50 0 16 9 0.0000 4 135 540 670 5600 CPU 3\001
+4 2 0 50 0 16 9 0.0000 4 135 540 670 5870 CPU 4\001
+4 2 0 50 0 16 9 0.0000 4 135 540 670 6140 CPU 5\001
+4 2 0 50 0 16 9 0.0000 4 135 540 670 6410 CPU 6\001
+4 2 0 50 0 16 9 0.0000 4 135 540 670 6680 CPU 7\001
+4 2 0 50 0 16 9 0.0000 4 135 540 670 6950 CPU 8\001
+4 2 0 50 0 16 9 0.0000 4 135 540 670 7220 CPU 9\001
+4 2 0 50 0 16 9 0.0000 4 135 540 670 7490 CPU 10\001
+4 2 0 50 0 16 9 0.0000 4 135 540 670 7760 CPU 11\001
+4 2 0 50 0 16 9 0.0000 4 135 540 670 8030 CPU 12\001
+4 2 0 50 0 16 9 0.0000 4 135 540 670 8300 CPU 13\001
+4 2 0 50 0 16 9 0.0000 4 135 540 670 8570 CPU 14\001
+4 2 0 50 0 16 9 0.0000 4 135 540 670 8840 CPU 15\001
+-6
+2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
+ 1485 4275 8190 4860
+2 1 0 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
+ 3915 4725 3915 9270
+2 1 1 1 0 7 50 -1 -1 4.000 0 0 -1 0 0 2
+ 720 4275 720 4860
diff --git a/advsync/MoreThanOneValue-15CPU.input b/advsync/MoreThanOneValue-15CPU.input
new file mode 100644
index 0000000..075a235
--- /dev/null
+++ b/advsync/MoreThanOneValue-15CPU.input
@@ -0,0 +1,16 @@
+0
+12 1 90 6 147 4 225 10 311 15 442 3 515 9 0 0 13 89 91 146 148 224 226 310 312 441 443 514 0 0
+16 2 441 3 510 9 0 0 17 440 443 509 0 0
+17 3 511 9 0 0 19 510 0 0
+15 4 212 10 294 15 391 12 475 9 0 0 16 211 335 390 400 474 0 0
+16 5 214 10 297 15 393 12 476 9 0 0 17 213 226 296 335 392 400 475 0 0
+17 6 173 2 333 15 500 9 0 0 18 172 174 332 335 499 0 0
+18 7 172 2 334 15 499 9 0 0 19 171 173 333 335 498 0 0
+15 8 25 9 0 0 16 24 0 0
+17 9 0 0 0 0
+21 10 308 15 397 12 472 9 0 0 226 307 335 396 400 471 0 0
+20 11 78 10 309 15 399 12 473 9 0 0 21 77 226 308 335 398 400 472 0 0
+13 12 525 9 0 0 400 524 0 0
+12 13 57 12 523 9 0 0 13 56 400 522 0 0
+13 14 20 15 379 12 528 9 0 0 14 19 400 527 0 0
+16 15 381 12 529 9 0 0 26 380 400 528 0 0
diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
index 4732172..dfbf0f3 100644
--- a/advsync/memorybarriers.tex
+++ b/advsync/memorybarriers.tex
@@ -352,152 +352,37 @@ CPU~4 believes that the value is ``4'' for almost 500ns.
} \QuickQuizEnd
And if you think that the situation with four CPUs was intriguing, consider
-Table~\ref{tab:advsync:A Variable With More Simultaneous Values},
+Figure~\ref{fig:advsync:A Variable With More Simultaneous Values},
which shows the same situation, but with 15 CPUs all assigning their
-number to a single shared variable at time $t=0$.
-The first column of the table shows the time measured in
-timebase ticks, with each such tick lasting about 5.3 nanoseconds.
+number to a single shared variable at time $t=0$. Both diagrams in the
+figure is drawn in the same way as
+Figure~\ref{fig:advsync:A Variable With Multiple Simultaneous Values}.
+The only difference is that the unit of horizontal axis is timebase ticks,
+with each tick lasting about 5.3 nanoseconds.
The entire sequence therefore lasts a bit longer than the events recorded in
Figure~\ref{fig:advsync:A Variable With Multiple Simultaneous Values},
consistent with the increase in number of CPUs.
-The remaining 15 columns in the table record the values most recently
-observed by the corresponding CPU at each point in time, with changes
-in value marked by italics and parentheses.
-Blank cells correspond to times when the CPU did not respond.
-Non-response could be due to the CPU waiting on a cache miss,
-the CPU being interrupted, the user-level thread being preempted,
-and so on.
+The upper diagram shows the overall picture, while the lower one shows
+the zoom-up of first 50 timebase ticks.
+
Again, CPU~0 coordinates the test, so does not record any values.
-\begin{table*}[htbp]
-\scriptsize
-\centering
-\begin{tabular}{r||c|c|c|c|c|c|c|c|c|c|c|c|c|c|c}
- & \multicolumn{15}{c}{CPU's Observed Values} \\
- \cline{2-16}
-Time & 1 & 2 & 3 & 4 & 5 & 6 & 7 & 8 & 9 & 10 & 11 & 12 & 13 & 14 & 15 \\
-\hline
-\hline
-12 & \emph{(1)} & & & & & & & & & & & & & & \\
-\hline
-12 & ~ & & & & & & & & & & & & \emph{(13)} & & \\
-\hline
-13 & ~ & & & & & & & & & & & \emph{(12)} & ~ & & \\
-\hline
-13 & ~ & & & & & & & & & & & 12 & ~ & \emph{(14)} & \\
-\hline
-15 & ~ & & & \emph{(4)} & & & & & & & & 12 & ~ & ~ & \\
-\hline
-15 & ~ & & & ~ & & & & \emph{(8)} & & & & 12 & ~ & ~ & \\
-\hline
-15 & ~ & & & ~ & & & & ~ & & & & 12 & ~ & ~ & \emph{(15)} \\
-\hline
-16 & ~ & \emph{(2)} & & ~ & & & & ~ & & & & 12 & ~ & ~ & 15 \\
-\hline
-16 & ~ & ~ & & ~ & \emph{(5)} & & & ~ & & & & 12 & ~ & ~ & 15 \\
-\hline
-17 & ~ & ~ & \emph{(3)} & ~ & ~ & & & ~ & & & & 12 & ~ & ~ & 15 \\
-\hline
-17 & ~ & ~ & 3 & ~ & ~ & \emph{(6)} & & ~ & & & & 12 & ~ & ~ & 15 \\
-\hline
-17 & ~ & ~ & 3 & ~ & ~ & ~ & & ~ & \emph{(9)} & & & 12 & ~ & ~ & 15 \\
-\hline
-18 & ~ & ~ & 3 & ~ & ~ & ~ & \emph{(7)} & ~ & 9 & & & 12 & ~ & ~ & 15 \\
-\hline
-20 & ~ & ~ & ~ & ~ & ~ & ~ & ~ & ~ & 9 & & \emph{(11)} & 12 & ~ & ~ & 15 \\
-\hline
-20 & ~ & ~ & ~ & ~ & ~ & ~ & ~ & ~ & 9 & & ~ & 12 & ~ & \emph{(15)} & 15 \\
-\hline
-21 & ~ & ~ & ~ & ~ & ~ & ~ & ~ & ~ & 9 & \emph{(10)} & ~ & 12 & ~ & 15 & 15 \\
-\hline
-25 & ~ & ~ & ~ & ~ & ~ & ~ & ~ & \emph{(9)} & 9 & 10 & ~ & 12 & ~ & 15 & 15 \\
-\hline
-57 & ~ & ~ & ~ & ~ & ~ & ~ & ~ & 9 & 9 & 10 & ~ & 12 & \emph{(12)} & 15 & ~ \\
-\hline
-78 & ~ & ~ & ~ & ~ & ~ & ~ & ~ & 9 & 9 & 10 & \emph{(10)} & 12 & 12 & 15 & ~ \\
-\hline
-90 & \emph{(6)} & ~ & ~ & ~ & ~ & ~ & ~ & 9 & 9 & 10 & 10 & 12 & 12 & 15 & ~ \\
-\hline
-147 & \emph{(4)} & ~ & ~ & ~ & ~ & ~ & ~ & 9 & 9 & 10 & 10 & 12 & 12 & 15 & ~ \\
-\hline
-172 & ~ & ~ & ~ & ~ & ~ & ~ & \emph{(2)} & 9 & 9 & 10 & 10 & 12 & 12 & 15 & ~ \\
-\hline
-173 & ~ & ~ & ~ & ~ & ~ & \emph{(2)} & ~ & 9 & 9 & 10 & 10 & 12 & 12 & 15 & ~ \\
-\hline
-212 & ~ & ~ & ~ & \emph{(10)} & ~ & ~ & ~ & 9 & 9 & 10 & 10 & 12 & 12 & 15 & ~ \\
-\hline
-214 & ~ & ~ & ~ & 10 & \emph{(10)} & ~ & ~ & 9 & 9 & 10 & 10 & 12 & 12 & 15 & ~ \\
-\hline
-225 & \emph{(10)} & ~ & ~ & 10 & 10 & ~ & ~ & 9 & 9 & 10 & 10 & 12 & 12 & 15 & ~ \\
-\hline
-294 & ~ & ~ & ~ & \emph{(15)} & ~ & ~ & ~ & 9 & 9 & ~ & ~ & 12 & 12 & 15 & ~ \\
-\hline
-297 & ~ & ~ & ~ & 15 & \emph{(15)} & ~ & ~ & 9 & 9 & ~ & ~ & 12 & 12 & 15 & ~ \\
-\hline
-308 & ~ & ~ & ~ & 15 & 15 & ~ & ~ & 9 & 9 & \emph{(15)} & ~ & 12 & 12 & 15 & ~ \\
-\hline
-309 & ~ & ~ & ~ & 15 & 15 & ~ & ~ & 9 & 9 & 15 & \emph{(15)} & 12 & 12 & 15 & ~ \\
-\hline
-311 & \emph{(15)} & ~ & ~ & 15 & 15 & ~ & ~ & 9 & 9 & 15 & 15 & 12 & 12 & 15 & ~ \\
-\hline
-333 & ~ & ~ & ~ & 15 & 15 & \emph{(15)} & ~ & 9 & 9 & 15 & 15 & 12 & 12 & 15 & ~ \\
-\hline
-334 & ~ & ~ & ~ & 15 & 15 & 15 & \emph{(15)} & 9 & 9 & 15 & 15 & 12 & 12 & 15 & ~ \\
-\hline
-379 & ~ & ~ & ~ & ~ & ~ & ~ & ~ & 9 & 9 & ~ & ~ & 12 & 12 & \emph{(12)} & ~ \\
-\hline
-381 & ~ & ~ & ~ & ~ & ~ & ~ & ~ & 9 & 9 & ~ & ~ & 12 & 12 & 12 & \emph{(12)} \\
-\hline
-391 & ~ & ~ & ~ & \emph{(12)} & ~ & ~ & ~ & 9 & 9 & ~ & ~ & 12 & 12 & 12 & 12 \\
-\hline
-393 & ~ & ~ & ~ & 12 & \emph{(12)} & ~ & ~ & 9 & 9 & ~ & ~ & 12 & 12 & 12 & 12 \\
-\hline
-397 & ~ & ~ & ~ & 12 & 12 & ~ & ~ & 9 & 9 & \emph{(12)} & ~ & 12 & 12 & 12 & 12 \\
-\hline
-399 & ~ & ~ & ~ & 12 & 12 & ~ & ~ & 9 & 9 & 12 & \emph{(12)} & 12 & 12 & 12 & 12 \\
-\hline
-441 & ~ & \emph{(3)} & ~ & ~ & ~ & ~ & ~ & 9 & 9 & ~ & ~ & ~ & ~ & ~ & ~ \\
-\hline
-442 & \emph{(3)} & 3 & ~ & ~ & ~ & ~ & ~ & 9 & 9 & ~ & ~ & ~ & ~ & ~ & ~ \\
-\hline
-472 & ~ & ~ & ~ & ~ & ~ & ~ & ~ & 9 & 9 & \emph{(9)} & ~ & ~ & ~ & ~ & ~ \\
-\hline
-473 & ~ & ~ & ~ & ~ & ~ & ~ & ~ & 9 & 9 & 9 & \emph{(9)} & ~ & ~ & ~ & ~ \\
-\hline
-475 & ~ & ~ & ~ & \emph{(9)} & ~ & ~ & ~ & 9 & 9 & 9 & 9 & ~ & ~ & ~ & ~ \\
-\hline
-476 & ~ & ~ & ~ & 9 & \emph{(9)} & ~ & ~ & 9 & 9 & 9 & 9 & ~ & ~ & ~ & ~ \\
-\hline
-499 & ~ & ~ & ~ & 9 & 9 & ~ & \emph{(9)} & 9 & 9 & 9 & 9 & ~ & ~ & ~ & ~ \\
-\hline
-500 & ~ & ~ & ~ & 9 & 9 & \emph{(9)} & 9 & 9 & 9 & 9 & 9 & ~ & ~ & ~ & ~ \\
-\hline
-510 & ~ & \emph{(9)} & ~ & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & ~ & ~ & ~ & ~ \\
-\hline
-511 & ~ & 9 & \emph{(9)} & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & ~ & ~ & ~ & ~ \\
-\hline
-515 & \emph{(9)} & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & ~ & ~ & ~ & ~ \\
-\hline
-523 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & ~ & \emph{(9)} & ~ & ~ \\
-\hline
-525 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & \emph{(9)} & 9 & ~ & ~ \\
-\hline
-528 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & \emph{(9)} & ~ \\
-\hline
-529 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & 9 & \emph{(9)} \\
-\end{tabular}
+\begin{figure*}
+\begin{center}
+\resizebox{5in}{!}{\includegraphics{advsync/MoreThanOneValue-15CPU}}
+\end{center}
\caption{A Variable With More Simultaneous Values}
-\label{tab:advsync:A Variable With More Simultaneous Values}
-\end{table*}
+\label{fig:advsync:A Variable With More Simultaneous Values}
+\end{figure*}
All CPUs eventually agree on the final value of 9, but not before
the values 15 and 12 take early leads.
Note that there are fourteen different opinions on the variable's value
-at time 20.
+at time 21 indicated by the vertical bar in the lower diagram.
Note also that all CPUs see sequences whose orderings are consistent with
the directed graph shown in
Figure~\ref{fig:advsync:Possible Global Orders With More Simultaneous Values}.
-Nevertheless, the table and figure both underscore the importance of
+Nevertheless, both figures underscore the importance of
proper use of memory barriers for code that cares about memory ordering.
\begin{figure}[htb]
diff --git a/utilities/MoreThanOneValue-15CPU.c b/utilities/MoreThanOneValue-15CPU.c
new file mode 100644
index 0000000..fa4e717
--- /dev/null
+++ b/utilities/MoreThanOneValue-15CPU.c
@@ -0,0 +1,185 @@
+/*
+ * MoreThanOneValue-15CPU.c: Convert memory order 15 CPU result into .fig
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, you can access it online at
+ * http://www.gnu.org/licenses/gpl-2.0.html.
+ *
+ * Copyright (c) 2016 Akira Yokosawa
+ */
+
+#include <stdio.h>
+
+#define CPU_NUM (15)
+#define MAX_CHANGE (15)
+#define TIM_WIDTH (15)
+#define MAX_TIME (550)
+#define RULER_TICK (50 * TIM_WIDTH)
+
+/* length unit is pixel in 1200 dpi */
+static const int fig_base = 700;
+static const int max_time = MAX_TIME;
+static const int fig_width = MAX_TIME * TIM_WIDTH;
+static const int bar_height = 270;
+
+/* array for color selection for each value */
+static const int color[CPU_NUM] = {
+ 4, 6, 31, 14, 2, 3, 16, 27, 7, 5, 29, 22, 20, 28, 12
+};
+static const int area_fill[CPU_NUM] = {
+ 25, 25, 25, 25, 25, 25, 25, 25, 15, 25, 25, 25, 25, 25, 25
+};
+
+/* local storage for value change */
+static int chg_time[CPU_NUM][MAX_CHANGE];
+static int chg_val[CPU_NUM][MAX_CHANGE];
+static int unresp_time_b[CPU_NUM][MAX_CHANGE];
+static int unresp_time_e[CPU_NUM][MAX_CHANGE];
+
+int main(void)
+{
+ int i, j, k;
+ int ret;
+ int next_time;
+ int mode;
+ int unresp_end;
+
+ /* read mode */
+ ret = scanf("%d ", &mode);
+ if (EOF == ret)
+ goto err_exit;
+ if (mode != 0 && mode != 1)
+ goto err_exit;
+ /* read value change data from stdin */
+ for (i = 0; i < CPU_NUM; i++) {
+ for (j = 0; j < MAX_CHANGE; j++) {
+ ret = scanf("%d ", &chg_time[i][j]);
+ if (EOF == ret)
+ goto err_exit;
+ ret = scanf("%d ", &chg_val[i][j]);
+ if (EOF == ret)
+ goto err_exit;
+ if (chg_time[i][j] == 0 || chg_val[i][j] == 0)
+ break;
+ }
+ for (j = 0; j < MAX_CHANGE; j++) {
+ ret = scanf("%d ", &unresp_time_b[i][j]);
+ if (EOF == ret)
+ goto err_exit;
+ ret = scanf("%d ", &unresp_time_e[i][j]);
+ if (EOF == ret)
+ goto err_exit;
+ if (unresp_time_b[i][j] == 0 || unresp_time_e[i][j] == 0)
+ break;
+ }
+ }
+ /* output preamble */
+ printf("#FIG 3.2\n");
+ printf("Landscape\n");
+ printf("Center\n");
+ printf("Metric\n");
+ printf("A4\n");
+ printf("100.00\n");
+ printf("Single\n");
+ printf("-2\n");
+ printf("1200 2\n");
+ printf("6 %d 0 %d %d\n", fig_base - 50, fig_base + fig_width + 50,
+ (bar_height * CPU_NUM) + 100);
+
+ /* output boxes for each CPU */
+ for (i = 0; i < CPU_NUM; i++) {
+ printf("2 2 0 1 0 0 50 0 15 0.000 0 0 -1 0 0 5\n");
+ printf("\t%d %d %d %d %d %d %d %d %d %d\n",
+ fig_base, bar_height * i,
+ fig_base + chg_time[i][0] * TIM_WIDTH, bar_height * i,
+ fig_base + chg_time[i][0] * TIM_WIDTH, bar_height * (i + 1),
+ fig_base, bar_height * (i + 1),
+ fig_base, bar_height * i
+ );
+ for (j = 0; j < MAX_CHANGE; j++) {
+ next_time = chg_time[i][j+1];
+ if (next_time == 0 || next_time >= MAX_TIME)
+ next_time = max_time;
+ printf("2 2 0 1 0 %d 50 0 20 0.000 0 0 -1 0 0 5\n", color[chg_val[i][j]-1]);
+ printf("\t%d %d %d %d %d %d %d %d %d %d\n",
+ fig_base + chg_time[i][j] * TIM_WIDTH, bar_height * i,
+ fig_base + next_time * TIM_WIDTH, bar_height * i,
+ fig_base + next_time * TIM_WIDTH, bar_height * (i + 1),
+ fig_base + chg_time[i][j] * TIM_WIDTH, bar_height * (i + 1),
+ fig_base + chg_time[i][j] * TIM_WIDTH, bar_height * i
+ );
+ /* if mode == 1, draw box for unresponsive state if there is */
+ if (mode == 1) {
+ for (k = 0; k < MAX_CHANGE; k++) {
+ if (unresp_time_b[i][k] == 0 || unresp_time_e[i][k] == 0)
+ break;
+ if (unresp_time_b[i][k] > chg_time[i][j] &&
+ unresp_time_b[i][k] < next_time) {
+ /* let's draw */
+ unresp_end = unresp_time_e[i][k];
+ if (unresp_end >= MAX_TIME)
+ unresp_end = max_time;
+ printf("2 2 0 0 0 %d 50 0 %d 0.000 0 0 -1 0 0 5\n",
+ color[chg_val[i][j]-1],
+ area_fill[chg_val[i][j]-1]
+ );
+ printf("\t%d %d %d %d %d %d %d %d %d %d\n",
+ fig_base + unresp_time_b[i][k] * TIM_WIDTH,
+ bar_height * i + 10,
+ fig_base + unresp_end * TIM_WIDTH,
+ bar_height * i + 10,
+ fig_base + unresp_end * TIM_WIDTH,
+ bar_height * (i + 1) - 10,
+ fig_base + unresp_time_b[i][k] * TIM_WIDTH,
+ bar_height * (i + 1) - 10,
+ fig_base + unresp_time_b[i][k] * TIM_WIDTH,
+ bar_height * i + 10
+ );
+ }
+ }
+ }
+ printf("4 1 0 50 0 18 9 0.0000 4 90 150 %d %d %d\\001\n",
+ fig_base + (chg_time[i][j] + next_time) / 2 * TIM_WIDTH,
+ bar_height * i + 200, chg_val[i][j]);
+ if (chg_time[i][j+1] == 0 || chg_time[i][j+1] >= MAX_TIME) break;
+ }
+ }
+ /* output ruler */
+ /* horiz line */
+ printf("2 1 0 2 0 7 50 0 -1 0.000 0 0 -1 1 0 2\n");
+ printf("\t1 1 1.00 60.00 120.00\n");
+ printf("\t %d %d %d %d\n", fig_base, bar_height * CPU_NUM + 200,
+ fig_base + max_time * TIM_WIDTH, bar_height * CPU_NUM + 200);
+ /* ruler ticks */
+ i = 0;
+ do {
+ printf("2 1 0 1 0 7 50 0 -1 0.000 0 0 -1 0 0 2\n");
+ printf("\t %d %d %d %d\n",
+ fig_base + RULER_TICK * i, bar_height * CPU_NUM + 150,
+ fig_base + RULER_TICK * i, bar_height * CPU_NUM + 250);
+ printf("4 1 0 50 0 16 9 0.0000 4 90 375 %d %d %d\\001\n",
+ fig_base + RULER_TICK * i, bar_height * CPU_NUM + 400,
+ (RULER_TICK * i)/TIM_WIDTH);
+ i++;
+ } while (RULER_TICK * i < fig_width);
+ /* label CPU */
+ for (i = 0; i < CPU_NUM; i++) {
+ printf("4 2 0 50 0 16 8.5 0.0000 4 105 420 %d %d CPU %2d\\001\n",
+ fig_base - 30, bar_height * i + 200, i + 1);
+ }
+ printf("-6\n");
+ return 0;
+
+err_exit:
+ fprintf(stderr, "error in input\n");
+ return 1;
+}
--
1.9.1
--
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