This commit fixes typos related with latex. The typos include:
missed tildes, doubly inserted commas, and incinsistently formatted code
citations.
Signed-off-by: SeongJae Park <sj38.park@xxxxxxxxx>
---
advsync/memorybarriers.tex | 16 ++++++++--------
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/advsync/memorybarriers.tex b/advsync/memorybarriers.tex
index c668f3c..47d910a 100644
--- a/advsync/memorybarriers.tex
+++ b/advsync/memorybarriers.tex
@@ -37,7 +37,7 @@ appears to guarantee that the assertion never fires.
After all, if \co{r1 != 1}, we might hope that Thread~1's load from \co{y}
must have happened before Thread~2's store to \co{y}, which might raise
further hopes that Thread~2's load from \co{x} must happen after
-Thread 1's store to \co{x}, so that \co{r2 == 1}, as required by the
+Thread~1's store to \co{x}, so that \co{r2 == 1}, as required by the
assertion.
The example is symmetric, so similar hopeful reasoning might lead
us to hope that \co{r2 != 1} guarantees that \co{r1 == 1}.
@@ -295,7 +295,7 @@ over a 532-nanosecond time period, as shown in
Figure~\ref{fig:advsync:A Variable With Multiple Simultaneous Values}.
This data was collected on 1.5GHz POWER5 system with 8 cores, each containing
a pair of hardware threads.
-CPUs~1, 2, 3, and 4 recorded the values, while CPU 0 controlled the test.
+CPUs~1, 2, 3, and~4 recorded the values, while CPU~0 controlled the test.
The timebase counter period was about 5.32ns, sufficiently fine-grained
to allow observations of intermediate cache states.
@@ -1039,10 +1039,10 @@ a few simple rules:
that variable's value.}
\item If one CPU does ordered stores to variables A and B,\footnote{
For example, by executing the store to A, a
- memory barrier, and then the store to B.},
+ memory barrier, and then the store to B.}
and if a second CPU does ordered loads from B and A,\footnote{
For example, by executing the load from B, a
- memory barrier, and then the load from A.},
+ memory barrier, and then the load from A.}
then if the second CPU's load from B gives the value stored
by the first CPU, then the second CPU's load from A must
give the value stored by the first CPU.
@@ -1903,9 +1903,9 @@ In the above example, CPU~2 perceives that \co{B} is 7,
despite the load of \co{*C}
(which would be \co{B}) coming after the \co{LOAD} of \co{C}.
-If, however, a data dependency barrier were to be placed between the load of C
-and the load of \co{*C} (i.e.: \co{B}) on CPU~2, again with initial values of
-{\tt \{B = 7, X = 9, Y = 8, C = \&Y\}}:
+If, however, a data dependency barrier were to be placed between the load of
+\co{C} and the load of \co{*C} (i.e.: \co{B}) on CPU~2, again with initial
+values of {\tt \{B = 7, X = 9, Y = 8, C = \&Y\}}:
\vspace{5pt}
\begin{minipage}[t]{\columnwidth}
@@ -2002,7 +2002,7 @@ Figure~\ref{fig:advsync:Read Barrier Supplied}.
\end{figure*}
To illustrate this more completely, consider what could happen if the code
-contained a load of A either side of the read barrier, once again
+contained a load of \co{A} either side of the read barrier, once again
with the same initial values of
{\tt \{A = 0, B = 9\}}:
--
1.9.1
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