On Tue, 2023-09-19 at 06:21 +1000, Ben Skeggs wrote:
> From: Ben Skeggs <bskeggs@xxxxxxxxxx>
>
> Adds support for allocating VIDEO_ENCODER classes from RM.
>
> Signed-off-by: Ben Skeggs <bskeggs@xxxxxxxxxx>
> ---
> drivers/gpu/drm/nouveau/include/nvif/class.h | 4 +
> .../drm/nouveau/include/nvkm/engine/nvenc.h | 2 +
> .../535.54.03/common/sdk/nvidia/inc/nvos.h | 7 ++
> .../nvidia/inc/kernel/gpu/intr/engine_idx.h | 4 +
> .../gpu/drm/nouveau/nvkm/engine/device/base.c | 10 ++
> .../gpu/drm/nouveau/nvkm/engine/fifo/r535.c | 1 +
> .../gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild | 4 +
> .../gpu/drm/nouveau/nvkm/engine/nvenc/ad102.c | 44 +++++++
> .../gpu/drm/nouveau/nvkm/engine/nvenc/ga102.c | 44 +++++++
> .../gpu/drm/nouveau/nvkm/engine/nvenc/priv.h | 3 +
> .../gpu/drm/nouveau/nvkm/engine/nvenc/r535.c | 110
> ++++++++++++++++++
> .../gpu/drm/nouveau/nvkm/engine/nvenc/tu102.c | 12 +-
> .../gpu/drm/nouveau/nvkm/subdev/gsp/r535.c | 4 +
> 13 files changed, 248 insertions(+), 1 deletion(-)
> create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/nvenc/ad102.c
> create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/nvenc/ga102.c
> create mode 100644 drivers/gpu/drm/nouveau/nvkm/engine/nvenc/r535.c
>
> diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h
> b/drivers/gpu/drm/nouveau/include/nvif/class.h
> index 17a8867648b9..86648c5d0dba 100644
> --- a/drivers/gpu/drm/nouveau/include/nvif/class.h
> +++ b/drivers/gpu/drm/nouveau/include/nvif/class.h
> @@ -231,6 +231,10 @@
> #define AMPERE_DMA_COPY_A
> 0x0000c6b5
> #define AMPERE_DMA_COPY_B
> 0x0000c7b5
>
> +#define NVC4B7_VIDEO_ENCODER
> 0x0000c4b7
> +#define NVC7B7_VIDEO_ENCODER
> 0x0000c7b7
> +#define NVC9B7_VIDEO_ENCODER
> 0x0000c9b7
> +
> #define FERMI_DECOMPRESS
> 0x000090b8
>
> #define NV50_COMPUTE
> 0x000050c0
> diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h
> b/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h
> index 1f6eef13f872..018c58fc32ba 100644
> --- a/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h
> +++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/nvenc.h
> @@ -13,4 +13,6 @@ struct nvkm_nvenc {
>
> int gm107_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int
> inst, struct nvkm_nvenc **);
> int tu102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int
> inst, struct nvkm_nvenc **);
> +int ga102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int
> inst, struct nvkm_nvenc **);
> +int ad102_nvenc_new(struct nvkm_device *, enum nvkm_subdev_type, int
> inst, struct nvkm_nvenc **);
> #endif
> diff --git
> a/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/in
> c/nvos.h
> b/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/in
> c/nvos.h
> index 5c1cad9bc5db..61b98109a1c8 100644
> ---
> a/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/in
> c/nvos.h
> +++
> b/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/common/sdk/nvidia/in
> c/nvos.h
> @@ -112,6 +112,13 @@ typedef struct
> NvU32 engineInstance; // Select NVDEC0 or NVDEC1
> or NVDEC2
> } NV_BSP_ALLOCATION_PARAMETERS;
>
> +typedef struct
> +{
> + NvU32 size;
> + NvU32 prohibitMultipleInstances; // Prohibit multiple
> allocations of MSENC?
> + NvU32 engineInstance; // Select MSENC/NVENC0 or
> NVENC1 or NVENC2
> +} NV_MSENC_ALLOCATION_PARAMETERS;
> +
> typedef struct
> {
> NvU32 index;
> diff --git
> a/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/nvidia/inc/kernel/gp
> u/intr/engine_idx.h
> b/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/nvidia/inc/kernel/gp
> u/intr/engine_idx.h
> index b5cc77ab05a3..5ed292000036 100644
> ---
> a/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/nvidia/inc/kernel/gp
> u/intr/engine_idx.h
> +++
> b/drivers/gpu/drm/nouveau/include/nvrm/535.54.03/nvidia/inc/kernel/gp
> u/intr/engine_idx.h
> @@ -32,6 +32,10 @@
>
> #define MC_ENGINE_IDX_CE9 24
>
> +#define MC_ENGINE_IDX_MSENC 38
> +
> +#define MC_ENGINE_IDX_MSENC2 40
> +
> #define MC_ENGINE_IDX_GSP 49
>
> #define MC_ENGINE_IDX_BSP 64
> diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
> b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
> index cc54cb3365d0..af072ebcc8fa 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
> @@ -2622,6 +2622,7 @@ nv172_chipset = {
> .fifo = { 0x00000001, ga102_fifo_new },
> .gr = { 0x00000001, ga102_gr_new },
> .nvdec = { 0x00000003, ga102_nvdec_new },
> + .nvenc = { 0x00000001, ga102_nvenc_new },
> .sec2 = { 0x00000001, ga102_sec2_new },
> };
>
> @@ -2652,6 +2653,7 @@ nv173_chipset = {
> .fifo = { 0x00000001, ga102_fifo_new },
> .gr = { 0x00000001, ga102_gr_new },
> .nvdec = { 0x00000003, ga102_nvdec_new },
> + .nvenc = { 0x00000001, ga102_nvenc_new },
> .sec2 = { 0x00000001, ga102_sec2_new },
> };
>
> @@ -2682,6 +2684,7 @@ nv174_chipset = {
> .fifo = { 0x00000001, ga102_fifo_new },
> .gr = { 0x00000001, ga102_gr_new },
> .nvdec = { 0x00000003, ga102_nvdec_new },
> + .nvenc = { 0x00000001, ga102_nvenc_new },
> .sec2 = { 0x00000001, ga102_sec2_new },
> };
>
> @@ -2712,6 +2715,7 @@ nv176_chipset = {
> .fifo = { 0x00000001, ga102_fifo_new },
> .gr = { 0x00000001, ga102_gr_new },
> .nvdec = { 0x00000003, ga102_nvdec_new },
> + .nvenc = { 0x00000001, ga102_nvenc_new },
> .sec2 = { 0x00000001, ga102_sec2_new },
> };
>
> @@ -2742,6 +2746,7 @@ nv177_chipset = {
> .fifo = { 0x00000001, ga102_fifo_new },
> .gr = { 0x00000001, ga102_gr_new },
> .nvdec = { 0x00000003, ga102_nvdec_new },
> + .nvenc = { 0x00000001, ga102_nvenc_new },
> .sec2 = { 0x00000001, ga102_sec2_new },
> };
>
> @@ -2765,6 +2770,7 @@ nv192_chipset = {
> .fifo = { 0x00000001, ga102_fifo_new },
> .gr = { 0x00000001, ad102_gr_new },
> .nvdec = { 0x0000000f, ad102_nvdec_new },
> + .nvenc = { 0x00000007, ad102_nvenc_new },
> .sec2 = { 0x00000001, ga102_sec2_new },
> };
>
> @@ -2788,6 +2794,7 @@ nv193_chipset = {
> .fifo = { 0x00000001, ga102_fifo_new },
> .gr = { 0x00000001, ad102_gr_new },
> .nvdec = { 0x0000000f, ad102_nvdec_new },
> + .nvenc = { 0x00000007, ad102_nvenc_new },
> .sec2 = { 0x00000001, ga102_sec2_new },
> };
>
> @@ -2811,6 +2818,7 @@ nv194_chipset = {
> .fifo = { 0x00000001, ga102_fifo_new },
> .gr = { 0x00000001, ad102_gr_new },
> .nvdec = { 0x0000000f, ad102_nvdec_new },
> + .nvenc = { 0x00000007, ad102_nvenc_new },
> .sec2 = { 0x00000001, ga102_sec2_new },
> };
>
> @@ -2834,6 +2842,7 @@ nv196_chipset = {
> .fifo = { 0x00000001, ga102_fifo_new },
> .gr = { 0x00000001, ad102_gr_new },
> .nvdec = { 0x0000000f, ad102_nvdec_new },
> + .nvenc = { 0x00000007, ad102_nvenc_new },
> .sec2 = { 0x00000001, ga102_sec2_new },
> };
>
> @@ -2857,6 +2866,7 @@ nv197_chipset = {
> .fifo = { 0x00000001, ga102_fifo_new },
> .gr = { 0x00000001, ad102_gr_new },
> .nvdec = { 0x0000000f, ad102_nvdec_new },
> + .nvenc = { 0x00000007, ad102_nvenc_new },
> .sec2 = { 0x00000001, ga102_sec2_new },
> };
>
> diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c
> b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c
> index 553658a20025..7257120386e8 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/r535.c
> @@ -596,6 +596,7 @@ r535_fifo_runl_ctor(struct nvkm_fifo *fifo)
> engn = nvkm_runl_add(runl, nv2080, &r535_gr,
> type, inst);
> break;
> case NVKM_ENGINE_NVDEC:
> + case NVKM_ENGINE_NVENC:
> engn = nvkm_runl_add(runl, nv2080,
> &r535_flcn, type, inst);
> break;
> case NVKM_ENGINE_SW:
> diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild
> b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild
> index 6dcb20d1d156..2c1495b730f3 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild
> +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/Kbuild
> @@ -2,3 +2,7 @@
> nvkm-y += nvkm/engine/nvenc/base.o
> nvkm-y += nvkm/engine/nvenc/gm107.o
> nvkm-y += nvkm/engine/nvenc/tu102.o
> +nvkm-y += nvkm/engine/nvenc/ga102.o
> +nvkm-y += nvkm/engine/nvenc/ad102.o
> +
> +nvkm-y += nvkm/engine/nvenc/r535.o
> diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/ad102.c
> b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/ad102.c
> new file mode 100644
> index 000000000000..1b4619ff9e8e
> --- /dev/null
> +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/ad102.c
> @@ -0,0 +1,44 @@
> +/*
> + * Copyright 2023 Red Hat Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person
> obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without
> limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom
> the
> + * Software is furnished to do so, subject to the following
> conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
> USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +#include "priv.h"
> +
> +#include <subdev/gsp.h>
> +
> +#include <nvif/class.h>
> +
> +static const struct nvkm_engine_func
> +ad102_nvenc = {
> + .sclass = {
> + { -1, -1, NVC9B7_VIDEO_ENCODER },
> + {}
> + }
> +};
> +
> +int
> +ad102_nvenc_new(struct nvkm_device *device, enum nvkm_subdev_type
> type, int inst,
> + struct nvkm_nvenc **pnvenc)
> +{
> + if (nvkm_gsp_rm(device->gsp))
> + return r535_nvenc_new(&ad102_nvenc, device, type,
> inst, pnvenc);
> +
> + return -ENODEV;
> +}
> diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/ga102.c
> b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/ga102.c
> new file mode 100644
> index 000000000000..6463ab8e5871
> --- /dev/null
> +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/ga102.c
> @@ -0,0 +1,44 @@
> +/*
> + * Copyright 2023 Red Hat Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person
> obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without
> limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom
> the
> + * Software is furnished to do so, subject to the following
> conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
> USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +#include "priv.h"
> +
> +#include <subdev/gsp.h>
> +
> +#include <nvif/class.h>
> +
> +static const struct nvkm_engine_func
> +ga102_nvenc = {
> + .sclass = {
> + { -1, -1, NVC7B7_VIDEO_ENCODER },
> + {}
> + }
> +};
> +
> +int
> +ga102_nvenc_new(struct nvkm_device *device, enum nvkm_subdev_type
> type, int inst,
> + struct nvkm_nvenc **pnvenc)
> +{
> + if (nvkm_gsp_rm(device->gsp))
> + return r535_nvenc_new(&ga102_nvenc, device, type,
> inst, pnvenc);
> +
> + return -ENODEV;
> +}
> diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/priv.h
> b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/priv.h
> index b097e3f2867b..7917affc6505 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/priv.h
> +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/priv.h
> @@ -18,4 +18,7 @@ extern const struct nvkm_nvenc_fwif
> gm107_nvenc_fwif[];
>
> int nvkm_nvenc_new_(const struct nvkm_nvenc_fwif *, struct
> nvkm_device *, enum nvkm_subdev_type,
> int, struct nvkm_nvenc **pnvenc);
> +
> +int r535_nvenc_new(const struct nvkm_engine_func *, struct
> nvkm_device *,
> + enum nvkm_subdev_type, int, struct nvkm_nvenc **);
> #endif
> diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/r535.c
> b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/r535.c
> new file mode 100644
> index 000000000000..8449b41c72db
> --- /dev/null
> +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/r535.c
> @@ -0,0 +1,110 @@
> +/*
> + * Copyright 2023 Red Hat Inc.
> + *
> + * Permission is hereby granted, free of charge, to any person
> obtaining a
> + * copy of this software and associated documentation files (the
> "Software"),
> + * to deal in the Software without restriction, including without
> limitation
> + * the rights to use, copy, modify, merge, publish, distribute,
> sublicense,
> + * and/or sell copies of the Software, and to permit persons to whom
> the
> + * Software is furnished to do so, subject to the following
> conditions:
> + *
> + * The above copyright notice and this permission notice shall be
> included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
> EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
> MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO
> EVENT SHALL
> + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM,
> DAMAGES OR
> + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
> OTHERWISE,
> + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
> USE OR
> + * OTHER DEALINGS IN THE SOFTWARE.
> + */
> +#include "priv.h"
> +
> +#include <core/object.h>
> +#include <subdev/gsp.h>
> +#include <engine/fifo.h>
> +
> +#include <nvrm/nvtypes.h>
> +#include <nvrm/535.54.03/common/sdk/nvidia/inc/nvos.h>
> +
> +struct r535_nvenc_obj {
> + struct nvkm_object object;
> + struct nvkm_gsp_object rm;
> +};
> +
> +static void *
> +r535_nvenc_obj_dtor(struct nvkm_object *object)
> +{
> + struct r535_nvenc_obj *obj = container_of(object,
> typeof(*obj), object);
> +
> + nvkm_gsp_rm_free(&obj->rm);
> + return obj;
> +}
> +
> +static const struct nvkm_object_func
> +r535_nvenc_obj = {
> + .dtor = r535_nvenc_obj_dtor,
> +};
> +
> +static int
> +r535_nvenc_obj_ctor(const struct nvkm_oclass *oclass, void *argv,
> u32 argc,
> + struct nvkm_object **pobject)
> +{
> + struct nvkm_chan *chan = nvkm_uchan_chan(oclass->parent);
> + struct r535_nvenc_obj *obj;
> + NV_MSENC_ALLOCATION_PARAMETERS *args;
> +
> + if (!(obj = kzalloc(sizeof(*obj), GFP_KERNEL)))
> + return -ENOMEM;
> +
> + nvkm_object_ctor(&r535_nvenc_obj, oclass, &obj->object);
> + *pobject = &obj->object;
> +
> + args = nvkm_gsp_rm_alloc_get(&chan->rm.object, oclass-
> >handle, oclass->base.oclass,
> + sizeof(*args), &obj->rm);
> + if (WARN_ON(IS_ERR(args)))
> + return PTR_ERR(args);
> +
> + args->size = sizeof(*args);
> + args->engineInstance = oclass->engine->subdev.inst;
> +
> + return nvkm_gsp_rm_alloc_wr(&obj->rm, args);
> +}
> +
> +static void *
> +r535_nvenc_dtor(struct nvkm_engine *engine)
> +{
> + struct nvkm_nvenc *nvenc = nvkm_nvenc(engine);
> +
> + kfree(nvenc->engine.func);
> + return nvenc;
> +}
Why is nvenc returned as void * when it's clearly always of type
struct nvkm_nvenc * ?
If it's sometimes necessary to convert it to a void-pointer I think it
would be better to do that by assigning to a void-pointer at the place
where r535_nvenc_dtor() is actually called. This void-pointer's
subsequent usage then would make it obvious why it's void *
Is it necessary to return it in an opaque form? If so, that should be
commented.
> +
> +int
> +r535_nvenc_new(const struct nvkm_engine_func *hw, struct nvkm_device
> *device,
> + enum nvkm_subdev_type type, int inst, struct
> nvkm_nvenc **pnvenc)
> +{
> + struct nvkm_engine_func *rm;
> + int nclass;
> +
> + for (nclass = 0; hw->sclass[nclass].oclass; nclass++);
> +
> + if (!(rm = kzalloc(sizeof(*rm) + (nclass + 1) * sizeof(rm-
> >sclass[0]), GFP_KERNEL)))
A variable for the size increases readability greatly here.
e.g., size_t nvkm_engine_total_size = ...
> + return -ENOMEM;
> +
> + rm->dtor = r535_nvenc_dtor;
> + for (int i = 0; i < nclass; i++) {
> + rm->sclass[i].minver = hw->sclass[i].minver;
> + rm->sclass[i].maxver = hw->sclass[i].maxver;
> + rm->sclass[i].oclass = hw->sclass[i].oclass;
> + rm->sclass[i].ctor = r535_nvenc_obj_ctor;
> + }
> +
> + if (!(*pnvenc = kzalloc(sizeof(**pnvenc), GFP_KERNEL))) {
> + kfree(rm);
> + return -ENOMEM;
> + }
> +
> + return nvkm_engine_ctor(rm, device, type, inst, true,
> &(*pnvenc)->engine);
> +}
> diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/tu102.c
> b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/tu102.c
> index 8a436b398749..933864423bb3 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/tu102.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/engine/nvenc/tu102.c
> @@ -23,12 +23,22 @@
>
> #include <subdev/gsp.h>
>
> +#include <nvif/class.h>
> +
> +static const struct nvkm_engine_func
> +tu102_nvenc = {
> + .sclass = {
> + { -1, -1, NVC4B7_VIDEO_ENCODER },
> + {}
> + }
> +};
> +
> int
> tu102_nvenc_new(struct nvkm_device *device, enum nvkm_subdev_type
> type, int inst,
> struct nvkm_nvenc **pnvenc)
> {
> if (nvkm_gsp_rm(device->gsp))
> - return -ENODEV;
> + return r535_nvenc_new(&tu102_nvenc, device, type,
> inst, pnvenc);
>
> return nvkm_nvenc_new_(gm107_nvenc_fwif, device, type, inst,
> pnvenc);
> }
> diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
> b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
> index eb82dad1f74e..8a1f7ef913e6 100644
> --- a/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
> +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/gsp/r535.c
> @@ -863,6 +863,10 @@ r535_gsp_intr_get_table(struct nvkm_gsp *gsp)
> type = NVKM_ENGINE_NVDEC;
> inst = ctrl->table[i].engineIdx -
> MC_ENGINE_IDX_NVDEC0;
> break;
> + case MC_ENGINE_IDX_MSENC ... MC_ENGINE_IDX_MSENC2:
> + type = NVKM_ENGINE_NVENC;
> + inst = ctrl->table[i].engineIdx -
> MC_ENGINE_IDX_MSENC;
> + break;
> default:
> continue;
> }
