Hi, I'm still working on getting the reclocking work done right. There are several parts I identify: - Pausing PFIFO (with its caches), pause PGRAPH and wait for idle - Stop some PLL (I guess it is more, physically disconnect them from the engines) using the 0xc040 register. - reclock memory - reclock the other engines - Make sure the display doesn't blow up Depending on the cards, I have completed all of the steps or none. Anyway, pausing PFIFO and PGRAPH works well on all the card I tested and so, I would like it to be pushed. I have a new theory upon the PLL_SUPERVISOR(0xc040) that I want to test. When I'm done with this, I'll put together a patch for it and continue on the other steps. Please provide me with some feedback on the patch or push it if nothing bothers you. Martin PS: I'm quite busy at the moment, I'll write an in-depth mail when I've verified my theories and got proper support on other cards than the nv86 ones.
