I asked this question on IRC, but my experience has been that IRC is variable in whether the right person sees the message, so I apologise for potentially breaking etiquette. I've recently been working with a Xilinx Zynq FPGA/ARM combined device, in which I wish to use DMA to transfer data from the FPGA side to the ARM side. Now, this is well supported at the kernel level. Xilinx have a driver that uses with the DMA engine subsystem In this email thread: http://www.spinics.net/lists/dmaengin/msg04599.html there was discussion about writing a userspace facing driver for presenting the DMAd data and the transactions. There wasn't much discussion, but one criticism seemed to be that there was no place for userspace facing DMA access and that there should be a driver that encapsulates each device that uses the relevant subsystem. The problem is, there isn't always a subsystem that fits every weird and wonderful new bit of hardware that someone might create, which is a pretty huge space of things when using FPGAs. What is the preferred way to solve this problem? It was suggested to me that the uio subsystem is the way to go, and I'm aware of this approach, but I don't fully understand how to use this. Does the uio handle the DMA through the DMA engine subsystem, or do I need to handle the DMA from userspace? If so, can I add this to the uio driver (to gain the benefits of the DMA engine). Is there a better way to present entirely new bits of hardware (and specifically hardware accessed through DMA) to userspace? Thanks, Henry
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