Hi, On Tue, May 20, 2014 at 6:28 AM, <Valdis.Kletnieks@xxxxxx> wrote: > On Tue, 20 May 2014 00:39:26 -0000, Chan Kim said: >> But still it's confusing. Can two virtual addresses from the "same process" >> (in init process, one for nocache pool, the other not) point to the same >> physical address? > > I'm not sure what you're trying to say there. In general, the hardware > tags like non-cacheable and write-combining are applied to physical addresses, > not virtual. AFAIK most processors with MMU have cache control bits built into page table entries, effectively controlling caching by virtual address. E.g. x86 has Write Through and Cache Disabled bits in its PTEs, ARM PTEs have bits B and C that determine caching and buffering of the page, etc. -- Thanks. -- Max _______________________________________________ Kernelnewbies mailing list Kernelnewbies@xxxxxxxxxxxxxxxxx http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
