oh, I'm answerting to my own question again..I've beeing following the initial sparc page table setup. Looks like the PMD table which has 64 entries are managed by 4 blocks of 16 entries and the allocation of PTE table is by each 16 entry-block at one time. This is populating only 1/4 of PMD table and connecting 16 64-entry PTE tables each time. regards, Chan 보낸 사람 : "Chan Kim" <ckim@xxxxxxxxxx> 보낸 날짜 : 2014-05-01 20:49:25 ( +09:00 ) 받는 사람 : kernelnewbies@xxxxxxxxxxxxxxxxx <kernelnewbies@xxxxxxxxxxxxxxxxx> 참조 : 제목 : about PMD_SHIFT value (22 or 18?) Hi, Hope someone could answer to this question.. As some of you know, SRMMU(Sparc Reference MMU in Sparc V8) uses top 8, 6, 6 bits of the linear address as PGT, PMD, PTE table index. so PGDIR_SHIFT is 24 and PMD_SHIFT is 18, and PTE_SHIFT is 12. (page size 4096) These shift values are for getting the index to into each table. But in http://lxr.free-electrons.com/source/arch/sparc/include/asm/pgtable_32.h#L35 #define PMD_SHIFT 22. and in http://lxr.free-electrons.com/source/arch/sparc/include/asm/page_32.h#L84 typedef struct { unsigned long pmdv[16]; } pmd_t; Why is it like this? (those sources are for sparc) I'm having some confusion from this.. Could someone please explain it or give me a good reference about this? Best regards, Chan _______________________________________________ Kernelnewbies mailing list Kernelnewbies@xxxxxxxxxxxxxxxxx http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies _______________________________________________ Kernelnewbies mailing list Kernelnewbies@xxxxxxxxxxxxxxxxx http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
