> I am trying to understand how the interrupt handler in arm working.By > looking at the code,what I understood,when an interrupt > happens arm disables the irq, saves the cpsr to spsr,save current pc > to lr and switches to irq mode. Yes, that's right. Important to understand that IRQ processor mode has its (mode-private) own sp, lr and spsr registers. Additionally, mode-private registers (sp, lr and spsr) are inaccessible from other modes. > So in case of interrupt it branches to the vector_irq and there it > saves some registers and depending on which context > its happened,it will call __irq_user or __irq_svc. But before that it > switches to the supervisory mode. That's right. In Linux Kernel the IRQ, Data Abort, Prefetch Abort, SWI and Undefined exceptions are handled in SVC processor mode. In Linux SVC processor mode of ARM CPU is called "Kernel mode". You have to switch to SVC processor mode from IRQ (and other processor modes) to enabled reentrant interrupts. Simplistically, it works like this: (1) IRQ exception is entered, (2) spsr_irq, r0 and lr_irq is saved on the private IRQ stack (its size is only 12 bytes), (3) 'vector_stub' macro check from what processor mode we got here - kernel mode or user mode - and calculates what to call __irq_user or__irq_svc and (4) the last thing it does 'movs pc, lr' which loads spsr_irq into cpsr and puts lr into pc (lr now contains __irq_svc or __irq_user and spsr_irq[4:0] contains SVC mode bits). Mind, that r0 points to private IRQ stack that contains original r0, lr_irq and spsr_irq. > Here I got confused,because in this case user registered handler will > be executed in supervisory mode. > I was thinking interrupt handler will always be executed in interrupt mode. As said above, interrupt handler is executed in kernel mode. This is must to support reentrant interrupts. --- Kosta _______________________________________________ Kernelnewbies mailing list Kernelnewbies@xxxxxxxxxxxxxxxxx http://lists.kernelnewbies.org/mailman/listinfo/kernelnewbies
