On Sat, Aug 6, 2011 at 10:56 AM, Mulyadi Santosa <mulyadi.santosa@xxxxxxxxx> wrote:
On Sat, Aug 6, 2011 at 23:59, subin gangadharanpersonal guess: cache line alignment?
<subingangadharan@xxxxxxxxx> wrote:
> Hi All,
> I have some doubts on the alignment requirement.It would be really
> helpful,if someone can shed some light on this.
> Why there are so many different types of alignment like 4 byte, 8 byte,16
> byte ?.My exact question is, in a 32 bit machine(I assume processor reads
> data in 4 bytes),how 16 byte alignment makes different from 4 byte alignment
> ?.How this will influence the processor performance ?.
... so the data all can be read in one read swipe.....
or in other hand, if several data has different access type (some are
read only, the rest are read/write), then by aligning them to
different cache line, they won't interfere to each other...since AFAIK
a write to even one bit in a cache line will update the whole cache
line. Other data in the same cache line will stay, they will be just
rewritten AFAIK.
I hope my guess is right :)
Thanks for your quick reply.I have one more question.
So in case of processor with read/write granularity of 4 byte access,just for understanding purpose imagine it's with out cache.So in that case any difference is there between 4byte and other 8byte,16 byte alignment.
--
regards,
Mulyadi Santosa
Freelance Linux trainer and consultant
blog: the-hydra.blogspot.com
training: mulyaditraining.blogspot.com
--
With Regards
Subin Gangadharan
Everything should be made as simple as possible,but not simpler.
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