2010/8/15 Parmenides <mobile.parmenides@xxxxxxxxx>:
> Hi,
>
> For each irq descriptor, there is a state bit IRQ_DISABLED
> indicating whether corresponding IRQ is masked. But, when checking the
> source code, I find that the function mask_and_ack_8259A(), which is
> responsible for acknowledge the PIC and mask corresponding bit in it,
> doesn't affect IRQ_DISABLED bit at all. Its code is as follows:
>
> handle_real_irq:
> if (irq & 8) {
> inb(PIC_SLAVE_IMR); /* DUMMY - (do we need this?) */
> outb(cached_slave_mask, PIC_SLAVE_IMR);
> outb(0x60+(irq&7),PIC_SLAVE_CMD);/* 'Specific EOI' to slave */
> outb(0x60+PIC_CASCADE_IR,PIC_MASTER_CMD); /* 'Specific
> EOI' to master-IRQ2 */
> } else {
> inb(PIC_MASTER_IMR); /* DUMMY - (do we need this?) */
> outb(cached_master_mask, PIC_MASTER_IMR);
> outb(0x60+irq,PIC_MASTER_CMD); /* 'Specific EOI to master */
> }
>
> While for IO APIC, there is no change of IRQ_DISABLED bit yet.
>
> move_irq(irq);
> if ((irq_desc[irq].status & (IRQ_PENDING | IRQ_DISABLED))
> == (IRQ_PENDING | IRQ_DISABLED))
> mask_IO_APIC_irq(irq);
> ack_APIC_irq();
>
> So, is there unconsistency between kernel data and the state of PIC?
>
/* Internal flags */
53#define IRQ_INPROGRESS 0x00000100 /* IRQ handler
active - do not enter! */
54#define IRQ_DISABLED 0x00000200 /* IRQ disabled -
do not enter! */
IRQ_DISABLED is used by internal code to indicate the status information.
The logic code is described in
http://lxr.linux.no/linux+v2.6.35/kernel/irq/handle.c.
The code you displayed is for programming the PIC 8259A. pls.
reference the datasheet provided by intel.
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>
--
Best Regards
Lin
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