On Wed, Sep 30, 2009 at 6:01 AM, Michal Ludvig <mludvig@xxxxxxxxxxxx> wrote:
> Peter Teoh wrote:
>> On Wed, Sep 30, 2009 at 11:47 AM, Michal Ludvig <mludvig@xxxxxxxxxxxx> wrote:
>>> Hi all,
>>>
>>> I've got a digital IO card hanging off an ISA bus in PC/104 system. I'm
>>> pushing data packets to it, usually 16-32 bytes per transfer, 100x per
>>> second.
>>>
>>> Apparently ISA bus clock is supposed to run at 8MHz and I expected to
>>> achieve somewhat close-to-that performance with my driver. To test the
>>> throughput I've got a simple loop in my kernel driver:
>>>
>>> uint8_t data = 0;
>>> while(loops--) {
>>> outb(data, iobase);
>>> data = ~data;
>>> }
>>>
>>> A frequency probe reveals that the port status is changing at roughly
>>> 250kHz (and other timing checks confirm it), which is far less than the
>>> expected 8MHz.
>>>
>>> I've got two questions:
>>> 1) Can I speed it up somehow?
>>
>> generally, port i/o programming is always slower than mmio, why don't
>> u consider that option?
>
> Good idea. However ... does mmio need support on the isa-card side?
>
> How do I map ioports 0x300-0x30B to some address accessible by readb() /
> writeb()?
>
> I can't work out the relation between isa address space (0xA0000 to
> 0x100000) and io ports (eg mine 0x300 to 0x30B range). What do I pass to
> ioremap() [?] to get the ports accessible by readb/writeb?
this knowledge is from datasheet. but this is beyond my level of
understanding....eg for ICH7 manual:
5.15
) ......... 179
5.16 IDE Controller (D31:F1)
...................................................................................
183
5.16.1 PIO Transfers
.......................................................................................
183
5.16.1.1 PIO IDE Timing Modes
............................................................. 184
5.16.1.2 IORDY
Masking.......................................................................
184
5.16.1.3 PIO 32-Bit IDE Data Port Accesses
............................................ 184
5.16.1.4 PIO IDE Data Port Prefetching and Posting
................................. 185
There is some info on PIO, and then throughout many other MMIO stuff:
00
5.19 USB UHCI Host Controllers (D29:F0, F1, F2, and F3)
............................................ 200
5.19.1 Data Structures in Main Memory
............................................................. 200
5.19.2 Data Transfers to/from Main Memory
....................................................... 200
5.19.3 Data Encoding and Bit Stuffing
............................................................... 200
5.19.4 Bus
Protocol.........................................................................................
200
5.19.4.1 Bit
Ordering............................................................................
200
5.19.4.2 SYNC Field
.............................................................................
201
5.19.4.3 Packet Field
Formats................................................................
201
5.19.4.4 Address
Fields.........................................................................
201
5.19.4.5 Frame Number Field
................................................................ 201
5.19.4.6 Data Field
..............................................................................
201
5.19.4.7 Cyclic Redundancy Check (CRC)
................................................ 201
5.19.5 Packet
Formats.....................................................................................
201
5.19.6 USB Interrupts
.....................................................................................
201
5.19.6.1 Transaction-Based Interrupts
.................................................... 202
5.19.6.2 Non-Transaction Based Interrupts
.............................................. 203
5.19.7 USB Power Management
........................................................................
204
5.19.8 USB Legacy Keyboard Operation
............................................................. 204
USB EHCI Host Controller
(D29:F7)....................................................................
207
5.20.1 EHC Initialization
..................................................................................
207
5.20.1.1 BIOS Initialization
...................................................................
207
5.20.1.2 Driver Initialization
.................................................................. 207
5.20.1.3 EHC
Resets.............................................................................
208
5.20.2 Data Structures in Main Memory
............................................................. 208
5.20.3 USB 2.0 Enhanced Host Controller DMA
................................................... 208
5.20.4 Data Encoding and Bit Stuffing
............................................................... 208
5.20.5 Packet
Formats.....................................................................................
208
5.20.6 USB 2.0 Interrupts and Error Conditions
.................................................. 209
5.20.6.1 Aborts on USB 2.0-Initiated Memory
Reads................................. 209
5.20.7 USB 2.0 Power Management
.................................................................. 210
5.20.7.1 Pause Feature
.........................................................................
210
5.20.7.2 Suspend Feature
.....................................................................
210
5.20.7.3 ACPI Device States
.................................................................. 210
5.20.7.4 ACPI System
States.................................................................
211
5.20.7.5 Mobile/Ultra Mobile Only Considerations
..................................... 211
5.20.8 Interaction with UHCI Host
Controllers..................................................... 211
5.20.8.1 Port-Routing Logic
...................................................................
211
5.20.8.2 Device Connects
.....................................................................
213
5.20.8.3 Device
Disconnects..................................................................
213
5.20.8.4 Effect of Resets on Port-Routing Logic
........................................ 214
if I were u, i think linux kernel source is still the best reference.....
>
> Michal
>
>
>
>
>
--
Regards,
Peter Teoh
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