On Wed, Sep 30, 2009 at 3:18 AM, Thomas Petazzoni <thomas.petazzoni@xxxxxxxxxxxxxxxxxx> wrote: > Le Wed, 30 Sep 2009 13:50:22 +0800, > Peter Teoh <htmldeveloper@xxxxxxxxx> a écrit : > >> generally, port i/o programming is always slower than mmio, why don't >> u consider that option? > > Well, it's rarely an option. Either the device is programmed through > PIO *or* through MMIO. And I suspect that most ISA devices can only be > programmed through PIO. > > Thomas > -- I search all the drivers under ide, char, and several other directories, and almost all the drivers which used ISA port I/O always have a corresponding memory mapped I/O. Perhaps u know of any drivers that used only port I/O but not memory mapped I/O? But the authoritative answer comes from Intel manual: "Implementing Industry Standard Architecture (ISA) with Intel®Express Chipsets" http://www.intel.com/Assets/PDF/whitepaper/318244.pdf And within it says: "The ISA protocol allows for memory-mapped transactions to components placed on the bus. In order to support these transactions it is, therefore, necessary to support memory-mapped transaction on the LPC bus. The LPC specification specifies that such transactions are supported on the LPC bus. Indeed, on all I/O Controller Hubs up to and including ICH5 support these transactions. From ICH6 onwards, however, support for these transactions has been removed. As a result, it is not possible to support ISA memory mapped transactions on an Intel® Express chipset." well.....I really cannot fully understand these statement.....what is the difference between LPC DMA and ISA DMA? (both effectively should offer MMIO right?) but in the ICH7 manual (Intel® I/O Controller Hub 7 (ICH7) Family Datasheet): http://www.intel.com/Assets/PDF/datasheet/313053.pdf The ICH7 supports LPC DMA (Desktop and Mobile Only), which is similar to ISA DMA, through the ICH7’s DMA controller. LPC DMA is handled through the use of the LDRQ# lines from peripherals and special encoding on LAD[3:0] from the host. Single, Demand, Verify, and Increment modes are supported on the LPC interface. Channels 0– 3 are 8-bit channels. Channels 5–7 are 16-bit channels. Channel 4 is reserved as a generic bus master request. and in another part of document: Each DMA channel is hardwired to the compatible settings for DMA device size: channels [3:0] are hardwired to 8-bit, count-by-bytes transfers, and channels [7:5] are hardwired to 16-bit, count-by-words (address shifted) transfers. ICH7 provides 24-bit addressing in compliance with the ISA-Compatible specification. Each channel includes a 16-bit ISA-Compatible Current Register which holds the 16 least-significant bits of the 24-bit address, an ISA-Compatible Page Register which contains the eight next most significant bits of address. So, since ICH7 is a modern chipset (my 1yr computer at least), ISA compatibility is always provided. Which means port I/O + MMIO is always available? -- Regards, Peter Teoh -- To unsubscribe from this list: send an email with "unsubscribe kernelnewbies" to ecartis@xxxxxxxxxxxx Please read the FAQ at http://kernelnewbies.org/FAQ
