2009/4/10 yihect <yihect@xxxxxxx>:
> Hi, all:
> Im my device, there are many registers resider in several banks, these
> registers are all
> accessed by one IOCTL cmd in my driver. And there are 2 or 3 tasks will
> access these registers simultaneously in app layer.
>
> So, my question is: Is there some common model to do this kind of
> concurrent control? Is there some sample as reference?
> Any suggestion will be welcome also.
>
I can only suggest samples, common model u have to slowly go through
file by file. But I am not sure what kind of "common" model u are
looking for - commonality based on what attributes? In the kernel
source's drivers subdirectory:
./gpio/mcp23s08.c:
* with either 16 bit registers or with two adjacent 8 bit banks.
./char/cs5535_gpio.c:
* Gets the register offset for the GPIO bank.
./char/stallion.c:
* Define the offsets within the register bank of a cd1400 based panel.
* Define the offsets within the register bank of a sc26198 based panel.
./acpi/acpica/exfldio.c:
if (acpi_ex_register_overflow(obj_desc->bank_field.bank_obj,
./acpi/acpica/dsfield.c:
* Use Info.data_register_node to store bank_field Op
* It's safe because data_register_node will never be used when
create bank field
./hwmon/w83627ehf.c:
/* The W83627EHF registers for nr=7,8,9 are in bank 5 */
./hwmon/w83792d.c:
but the driver only accesses registers in bank 0, so we don't have
./hwmon/w83791d.c:
(index 0x4e), but the driver only accesses registers in bank 0. Since
./hwmon/w83627hf.c:
/* The W83782D registers for nr=7,8 are in bank 5 */
./i2c/chips/max6875.c:
The MAX6875 has a bank of registers and two banks of EEPROM.
./usb/host/sl811-hcd.c:
* - performance work; use both register banks; ...
/* for now, use only one transfer register bank */
./usb/gadget/ci13xxx_udc.c:
/* ctrl register bank access */
/* register bank descriptor */
./video/amifb.c:
#define BPC3_BANK2 (0x8000) /* Bits to select color register bank */
./rtc/rtc-cmos.c:
/* Most newer x86 systems have two register banks, the first used
./net/eepro.c:
ID_REG (register 2 of bank 0) */
register 2 of bank 0) to be sure. */
./net/smc91x.c:
* From this point the register bank must _NOT_ be switched away
* register to bank 1, so I can access the base address
./net/eth16i.c:
/* Now switch to register bank 2, for run time operation */
./net/lib8390.c:
* a page register that controls bank and packet buffer access. We guard
./net/enc28j60.c:
u8 bank; /* current register bank selected */
* select the current register bank if necessary
./net/pcmcia/smc91c92_cs.c:
DEBUG(3, " Restoring saved registers mask %2.2x bank %4.4x"
./net/pcmcia/fmvj18x_cs.c:
#define NODE_ID 8 /* node ID register (bank 0) */
#define MAR_ADR 8 /* multicast address registers (bank 1) */
#define DATAPORT 8 /* buffer mem port registers (bank 2) */
./net/pcmcia/axnet_cs.c:
* a page register that controls bank and packet buffer access. We guard
./net/pcmcia/nmclan_cs.c:
/* Switch MACE register bank (only 0 and 1 are valid) */
Reads a MACE register. This is bank independent; however, the
Writes to a MACE register. This is bank independent; however,
./net/smc9194.c:
hurt. This time, I need to switch the bank register to bank 1,
./net/tsi108_eth.c:
void __iomem *phyregs; /* Base of register bank used for PHY access */
./net/at1700.c:
/* Run-time register bank 2 definitions. */
/* Powerup, switch to register bank 2, and enable the Rx and Tx. */
./net/irda/smsc-ircc2.c:
static inline void register_bank(int iobase, int bank)
etc.etc.....many others.
--
Regards,
Peter Teoh
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