On Sat, Feb 21, 2009 at 3:05 AM, wp158042-1 <ole@xxxxxxxxxxxxx> wrote:
>
> Hello there,
>
> I'm trying to handle a timer interrupt within the at91 processor...
>
> The Problem is: nothing happens, my interrupt handler is never called...
>
> Maybe someone here knows about the at91...
>
> this is my setup routine:
>
> static int __init ad_irq_init(void)
> {
> unsigned int ret;
>
> printk(KERN_INFO "init timer");
>
> // unsigned int base, unsigned int reg_offset, unsigned long value
>
> // disable clock:
> printk(KERN_INFO "ccr: %i\n", (unsigned int)at91_sys_read(AT91_TC_CCR) );
> at91_sys_write(AT91_TC_CCR, (at91_sys_read(AT91_TC_CCR) | 2) );
> printk(KERN_INFO "ccr: %i\n", (unsigned int)at91_sys_read(AT91_TC_CCR) );
>
> // disable all interrupts:
> at91_sys_write(AT91_TC_IDR, 0xFFFFFFFF );
>
> // enable timer clock 5, reset counter and start clock
> at91_sys_write(AT91_TC_CMR, 0x4 | 0x4000 );
>
> // enable clock :
> at91_sys_write(AT91_TC_CCR, 0x1 );
>
> // Enables the RC Compare Interrupt. :
> at91_sys_write(AT91_TC_IER, 0x10 );
>
>
> // set isr
> //at91_sys_write( AT91_AIC_SVR(6), timer_interrupt);
> // setup_irq(AT91_ID_TC0, &timer_interrupt);
> if (request_irq(AT91_ID_TC0, (void *)ad_irq_interrupt, SA_INTERRUPT
> ,AD_IRQ_DEVICE_NAME, NULL)) {
> printk(KERN_ERR "ad_irq: irq alrdy claimed!\n");
> return -EIO;
> }
>
> // write something to timer register c (taken from sample code without OS
> support):
> at91_sys_write( AT91_TC_RC , 0xFBC5 );
>
> at91_sys_write(AT91_TC_CCR , 0x4 );
>
> // set capture mode:
> at91_sys_write(AT91_TC_CMR, (0 << 15) );
>
i really know nuts about AT91, but from ./arch/arm/mach-at91/at91x40_time.c:
void __init at91x40_timer_init(void)
{
unsigned int v;
at91_sys_write(AT91_TC + AT91_TC_BCR, 0);
v = at91_sys_read(AT91_TC + AT91_TC_BMR);
v = (v & ~AT91_TC_TC1XC1S) | AT91_TC_TC1XC1S_NONE;
at91_sys_write(AT91_TC + AT91_TC_BMR, v);
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR,
AT91_TC_CLKDIS);
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CMR,
(AT91_TC_TIMER_CLOCK4 | AT91_TC_CPCTRG));
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IDR, 0xffffffff);
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_RC,
(AT91X40_MASTER_CLOCK / 128) / HZ - 1);
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_IER, (1<<4));
setup_irq(AT91X40_ID_TC1, &at91x40_timer_irq);
at91_sys_write(AT91_TC + AT91_TC_CLK1BASE + AT91_TC_CCR,
(AT91_TC_SWTRG | AT91_TC_CLKEN));
}
it seemed there is either:
1. some missing registers not setup.
2. or some of the register setup got its order wrong.
--
Regards,
Peter Teoh
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