Hi,
On Sun, Feb 22, 2009 at 8:25 AM, Grant Grundler
<grundler@xxxxxxxxxxxxxxxx> wrote:
> On Fri, Feb 20, 2009 at 07:10:24AM -0700, Matthew Wilcox wrote:
>> On Fri, Feb 20, 2009 at 07:09:51PM +0530, arun c wrote:
>> > PCI host machine (PPC cpu) writes commands to
>> > the PCI memory space of the (Coldfire CPU)
>> > target device. Target device takes the command
>> > and executes it.
>> >
>> > Target devices SDRAM is exposed over PCI to host.
>> > A circular buffer residing on target memory is used
>> > for command exchange.
>> >
>> > I should not allow host and target to play on the
>> > buffer simultaneously in order to avoid corruption.
>> >
>> > Does anybody know how to implement a lock
>> > suitable for this issue?
>> >
>> > or any lock less algorithm exists for communication
>> > over PCI?
>>
>> I would have thought that a standard head and tail lockless queue would
>> be perfect for your application. Expressed in C:
Yes I don't need any lock to protect my data
here, as host is write only and target is read only.
Here is what I did.
typedef command_pkt {
u32 valid;
......
......
......
u32 data[];
}
typedef struct my_circ_buf {
u32 read_index;
u32 write_index;
command_pkt_t cmd_pkt[30];
} my_circ_buf_t;
Host writes commands,makes valid
field to VALID,and increments write_index.
Target reads commands at read_index,
if and only if valid field is VALID and
after processing it makes valid field
INVALID and increments read_index.
It seems to be working for me
I need to investigate further for any
cache coherency issues, write now
I am running with dcache off.
Regards,
Arun C
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