On 13:22 Thu 11 Dec , Ranjan Sinha wrote:
> All interrupt processing happening only on CPU0. Installing older
> irqbalance does not seem to be an option here. What could be the
> reason. Is there a bug in APIC? Or am I missing something?
It means irqbalance daemon is disabled by default in your kernel.
It is recommended that you disable it for better performance
(or system interactivity).With this all IRQs are handled
by a single CPU (CPU0) in SMPs. Dedicating a subset of CPUs
to handle all IRQ's minimizes latencies in serving them
as it reduces cache line bouncing.
I hope that helps.
-
Rahul
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