On Thu, Oct 30, 2008 at 11:07 PM, Peerless Deepak <peerlessdriver@xxxxxxxxx> wrote:
Hi ,
Sorry forgot to append the question.
Can you point me to the kernel code where resource allocation is done
On Fri, Oct 31, 2008 at 8:58 AM, Peerless Deepak
<peerlessdriver@xxxxxxxxx> wrote:
> Hi All,
>
> I am trying to reassign bus numbers and configure BAR's from kernel by
> setting PPC_PCI_REASSIGN_ALL_BUS flag.
>
> pcibios_assign_resources - fills up the device structure by reading
> the BARs . I am trying to locate the part of the code which actually
> fills up the BAR.
and BAR's are filled?
Does anyone have an answer to this question? Greg?
I'm curious to know if this can be done on the x86 too. I know that currently even if a PCI device does claim to support 64-bit BARs, the BIOS will still allocate the BARs under 4GB. I really want to build a custom (test) kernel that can reassign the BARs to > 4GB, and not depend on the BIOS to do that.
I think this is more complicated than simply writing a new BAR base into the PCI device's config space register.
1) How do we ensure that we're not overlapping the physcal address space of any other PCI device when we choose a new BAR? Thinking about it, I guess we can use the physical address-space map that Linux gets with int15/E820h to see which physical memory areas are unused. Does that also report memory maps for regions above 4GB?
2) I've just skimmed over the datasheet for one chiset controller, the Intel GMCH35. I think the "decode window" of the Host-PCI bridge in the chipset will also have to be reconfigured so that it will direct Host accesses to the new BAR range to the PCI express link. Or will it intercept config writes to the BAR portion of the PCI device's config space and update itself?
Thanks in advance for your answers. I find this stuff extremely intriguing! :)
-Mayank
