Thank you Pranav and Mulyadi, On 7/6/08, Pranav Peshwe <pranavpeshwe@xxxxxxxxx> wrote: > > On Sat, Jul 5, 2008 at 8:40 PM, Mulyadi Santosa <mulyadi.santosa@xxxxxxxxx> > wrote: > > Guessing.. > > > > > > On Thu, Jul 3, 2008 at 11:19 PM, Peter Teoh <htmldeveloper@xxxxxxxxx> > wrote: > > > http://lkml.org/lkml/2007/1/5/213 > > > > > > Question here is: what is CR3 caching? (few first line of email)? > > > > probably it means it is stored in somekind of "fake" CR3 register. As > > you know that storing/reading something to/from RAM is expensive > > compared to accessing registers, so if you can "cache" them in > > register, it would be damn faster... > > > > Note, that's VT feature...meaning it is used for virtualization. That > > makes sense, because vm exit/enter might happen so many times....and > > that includes switching between many CR3 furiously....multiple times > > more frequently than normal context switching between processes. > > > > Hello, > From Ingo Molnar's mail (which starts that thread), what i could > infer is: > As Mulyadi states, CR3 caching is used during virtualization. Normally, any > change in CR3 would cause a switch out of the VMX mode into the hypervisor. > But, Intel seems to have employed a 4 entried cache which can be made to > store CR3 values for processes running in the guest. If, the changed CR3 > value is one of the 4 in the 'CR3 target cache' then, an expensive VM exit > to the hypervisor is avoided. > This is how, i guess, the KVM trunk+paravirt/c3 performance is 'faster by a > factor of 4' as compared to KVM trunk for 2 tasks and, decreases by a > considerable amount for more than 4 tasks. > > HTH. Kindly CMIIW. > > Best regards, > Pranav > I think you are right and I just extracted out the the entire section 20.6.7 from manual 3b here (but note that there is no "CR3 cache" mentioned, anyway): The VM-execution control fields include a set of 4 CR3-target values and a CR3-target count. The CR3-target values each have 64 bits on processors that support Intel EM64T and 32 bits on processors that do not. The CR3-target count has 32 bits on all processors. An execution of MOV to CR3 in VMX non-root operation does not cause a VM exit if its source operand matches one of these values. If the CR3-target count is n, only the first n CR3-target values are considered; if the CR3-target count is 0, MOV to CR3 always causes a VM exit There are no limitations on the values that can be written for the CR3-target values. VM entry fails (see Section 22.2) if the CR3-target count is greater than 4. Future processors may support a different number of CR3-target values. Software should read the VMX capability MSR IA32_VMX_MISC (see Appendix G.5) to determine the number of values supported. -- Regards, Peter Teoh -- To unsubscribe from this list: send an email with "unsubscribe kernelnewbies" to ecartis@xxxxxxxxxxxx Please read the FAQ at http://kernelnewbies.org/FAQ
