a. Access to main memory by devices vs CPU is sequentially accessed - possible or right
Not necessarily. A device and CPU can be accesing two different memory banks. If you look at the multi layered bus architectures different ports of the memory controller could be connected to the CPU and the master devices.
there is no worry on the CPU/linux kernel side about concurrently accessing a block of memory that is being updated by h/w devices at the same time. Correct?
Correct, u cannot access concurrently the same block of memory.
b. And in dual core/quadcore, there is still only one system bus is shared among the 4 CPU - for Intel north-south bridge architecture, right? But in AMD hypertransport the different parts of the memory can be accessed at the same time by different CPU? (NUMA?)
No idea.
c. Supposed there are N h/w devices wanting to access the main mem via DMA, so all of them have to go through a DMA controller for memory mapping. So it is impt on the software or BIOs side to ensure that the physical address allocated to these devices does not collide among themselves, correct? Is this done in kernel and/or BIOs?
To my knowledge the physical addresses are assigned neither by kernel nor by the BIOS(of the CPU).The hardware/firmware within dictate the adresses for the system layout.
Somebody please clarify this.
Regards,
Srinivas Bakki
