Re: Page faults in interrupt context

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On 18-11-07 18:30, Peter Teoh wrote:

Rene is right.

And don't you forget it...

What is the purpose of the IF flag then? (since it define the 0-31 range
of interrupts that can be masked out - and pagefault is one of them, and
yet it cannot be disabled/masked out)   Really confusing....at least for
me:-).

No, the IF flag is not limited to masking interrupts 0-31 or anything. As also gone into via private mail, clearing IF causes the CPU to ignore input on it's INTR pin.

(discussing the legacy PC only here)

Normally when the CPU is signalled on INTR by the external interrupt controller (PIC - Programmable Interrupt Controller) to which it is connected it starts a special bus-cycle to which the PIC responds by providing the "vector", the number, to the CPU.

Which number it provides is among the programmable aspects of the PIC and Linux programs it to provide vectors 0x20 to 0x2F for IRQs 0 to 15.

So say you hit a key on your (non USB...) keyboard. This causes the keyboard to send the keycode to the keyboard controller on your motherboard which then assert its IRQ line. That line is connected to the IRQ1 line on the Intel 8259A PIC (*) and, assuming the line is not disabled and no higher priority IRQ is active, the PIC then signals the CPU's INTR line and provides the 0x21 to the CPU that Linux told it it should provide for IRQ1. Upon receiving that 0x21, the CPU then calls the associated handler as it finds it in the IDT.

With IF cleared, the CPU simply ignores input on the INTR pin. So the purpose of the IF flag is quite a bit: it controls if the CPU recognizes any external interrupts.

These days things are or are getting to be different with the use of a Local APIC on semi-modern CPUs, I/O APIC on the motherboard, MSI (Message Signaled Interrupts) and lots of other fun but the above is what you should know about the flow of things.

(*) and what you do _not_ need to know that it's not just one 8259A but actually two daisy-chained ones -- and not actual ones, but their functional equivalents in integrated chipsets.

Hope this helps.

Rene.

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