Hi...
I can't understand why memory barrier must be used.
/* comment */
asmlinkage long sys_getppid(void)
{
int pid;
struct task_struct *me = current;
struct task_struct *parent;
parent = me->group_leader->real_parent;
for (;;) {
pid = parent->tgid;
#if defined(CONFIG_SMP) || defined(CONFIG_PREEMPT)
{
struct task_struct *old = parent;
/*
* Make sure we read the pid before re-reading the
* parent pointer :
*/
smp_rmb(); <----- Why ?
parent = me->group_leader->real_parent;
if (old != parent)
continue;
}
#endif
break;
}
return pid ;
}
First, be aware that the barrier is done only when SMP support *or* full
kernel level preemption is enabled.
Then (from my limited knowledge), we make sure that processor really
fetch the value of parent->tgid and then assign it
to "pid". In x86 arch, maybe it is not a big deal since x86 enforce
strict ordering. However, AFAIK certain arch like Alpha can freely
reorder read and write operation, thus we might read a stale value (not
the latest update).
In UP or non preemption enabled, this might not a big concern since a
kernel mode structure won't be accessed by more than one kernel path.
But in SMP or preemption enabled, thing goes the opposite. So, in the
middle of accessing a pointer, another code path could cross in, update
it and the control goes back to the first path. Thus again, in order to
make sure we read latest update (not the cached one in local L1/L2
cache), smp_rmb() must be issued.
regards,
Mulyadi
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