Rajendra Stalekar wrote:
Rajendra :- How can that be done? Is it not a physical interrupt
line(wire),
how can that line go to multiple devices.
That is the job of interrupt controller in the hardware- it multiplexes
the interrupt sources and presents them on the single interrupt number
IRQ number shown in /proc/interrupts. The way it is implemented in the
hardware differs for each architecture. When dealing with the shared
interrupts, the interrupt handler for each device driver needs to know
what hardware device caused the interrupt by means of dev_id argument
which must be unique for every device that claims the same interrupt
line (IRQ number) - hence every shared interrupt handler checks if the
interrupt was caused by the device it supports and handles the interrupt
only if it is from its device - otherwise the interrupt handler should
return IRQ_NONE and possibly let another (correct) device driver handle
the interrupt and return IRQ_HANDLED.
Rajendra :- Thanks a lot for explanation, however what I still haven't got
is, if the interrupt line needs to be shared, since it's a hardware stuff,
shouldn't the same interrupt line have 2 wires going from the same line, one
for one device and the other for the 2nd device. How , otherwise how will it
share the interrupt line?
I am aware of the other things, that u have mentioned here.
It is the job of the interrupt controller to take several physical
lines, or PCB traces if you wish, each leading to *only* one device and
multiplex those lines so that operating system sees them on a single IRQ
number.
For example take LX100 etrax CPU [1] (which I'm familiar with) that has
eight physical pins - grouped together in a port called port A. Each pin
of port A can be used as interrupt source and can connected to a
different device. OS OTOH sees complete port A (8 all pins) on a single
IRQ number 11. In order to assert which device caused the IRQ11 one
needs to inspect interrupt status register of port A and its bits to
determine which device actually caused the IRQ11. Several devices can
assert the IRQ11 at the same time and once all the set bits in interrupt
status register have been cleared all the devices have been handled.
regards,
hinko
[1] www.axis.com
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