On 5/4/07, k b <k_bisla@xxxxxxxxxxx> wrote:
Rajat, Thanks, l appreciate the insight. > The interrupts are disabled at the interrupt controller while kernel > is handling an IRQ. So any new interrupt generated before the kernel > handles the old interrupt will be lost. > I'm a little confused with your comment above. "INT lost while kernel processing the last INT". I would think it won't be lost, maybe more like delayed in processing. Doesn't the interrupt controller send the INT when the kernel re-enables the INT again. With what u are suggesting we would lose INT a lot.
Yes ,IIRC we discussed few days back this thing, but didn't quite hit the conclusion. IMHO maskable interrupts are disabled and thus cannot be served to the CPU but they can be buffered in the APIC. the moment INT pin is enabled again the interrupts are passed on to the CPU by the APIC. thoughts, anybody? Thank you ~psr
what do u thhink ? Anybody else, any comments ? Thanks, Bisla ________________________________ Connect to the next generation of MSN Messenger Get it now!
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