Hi kb,
at time T0 d3 fires an interrupt 5 at T1 d1 also fires an interrupt. and finally at T2 the kernel finds out (or gets ready to service the int) that int 5 was fired. Kernel starts iterating its list of handlers and call d1's INT handler. d1's INT services the interrupt and returns INT_HANDLED (even though device d1 wasn't the first to fire an Interrupt to start with). but the int line is still high/low(d3's int hasn't been handled yet),
The interrupts are disabled at the interrupt controller while kernel is handling an IRQ. So any new interrupt generated before the kernel handles the old interrupt will be lost.
Actually as i was re-reading it, i just realized d3 won't have a wait a lot longer as any time an INT comes in kernel would go though all the ISRs ( no matter what order they came in) only thing what matters is like you, Mike said is to make sure the ISR are as quick as possible.
Yes. Thanks, Rajat -- To unsubscribe from this list: send an email with "unsubscribe kernelnewbies" to ecartis@xxxxxxxxxxxx Please read the FAQ at http://kernelnewbies.org/FAQ
