On Saturday 26 August 2006 11:53, liang yuanen wrote:
> #define flush_cache_all() do { } while (0)
> #define flush_cache_mm(mm) do { } while (0)
> #define flush_cache_range(mm, start, end) do { } while (0)
> #define flush_cache_page(vma, vmaddr) do { } while (0)
> #define flush_page_to_ram(page) do { } while (0)
> #define flush_dcache_page(page) do { } while (0)
> #define flush_icache_range(start, end) do { } while (0)
> #define flush_icache_page(vma,pg) do { } while (0)
> #define flush_icache_user_range(vma,pg,adr,len) do { } while (0)
>
> all CPU cache operation is NULL for intel , This is mean in intel
> architecture, we do not touch CPU cache derectly, CPU cache all manage by
> hardware?
Yes, Intel has hardware that snoops the bus and makes sure that devices which
directly access the memory are in sync with the CPU cache. The concept is
similar to cache coherency protocols:
http://en.wikipedia.org/wiki/Cache_coherency
but instead of having as clients multiple processors, we have as clients the
CPU and the devices which can directly access memory.
tavi
--
Kernelnewbies: Help each other learn about the Linux kernel.
Archive: http://mail.nl.linux.org/kernelnewbies/
FAQ: http://kernelnewbies.org/faq/
