John Sony wrote:
Hi,
Why is that we disable the data cache when we write the bootloader.
Is it in anyway dependent on the MMU?
[Your question is severely lacking in details.]
In most CPUs instruction and data caches are not kept coherent. Thus, when
storing insns via ordinary writes to memory, e.g. in a bootloader or setting
breakpoints or preparing stack trampolines, the written insns go in data cache
and may not be "visible" to the insn cache when we attempt to execute the just
written code. So, either data cache is disabled or, after writing the code, data
cache is flushed (i.e. insns go to main memory) and insn cache is invalidated
(i.e. up to date insns are read from main memory).
~velco
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