final kernel page table setup -- Bover and Cesati doubt

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Hi

  googling on this didnt give me any useful links. Wld
appreciate if someone throws some light on this.

   section 2.5.5.2 in Bover and Cesati - UTLK , talks
about the final kernel page table, with different
sizes of physical RAM.
  case a), less than 896 MB, there the code for this
is ...

    address = 0xc0000000;
    while (address < end) {
         pe = ....;
         set_pgd(pgd, __pgd(pe));
         ++pe;
         address += 0x400000;
    }

    here it is said that, address+=0x400000 line
appears because the page size is 4MB.
   Similarly for the > 4GB case theres a corresponding
line address+=)x200000(this time for page middle
directory entry.
   
   Qestion : (taking case 1)Is this line there because
the page size is 4MB or because, a page table
dreictory entry points to a page table( 2 level
paging), 10 bits are devoted to the page table(hence
each table has 1024 entries), and the offset(assuming
it to be 12 bits) makes PAGE_SIZE to be 4KB, hence one
page directory entry points to )xc0000000, and the
next points to an address 2^22= 4MB away.
     Similarly in the second case, the page size is
not necessarily 2 MB, instead if it is 4KB, and page
table has 512 entries(2^9), says that the next entry
in pmd, shld point to a location , 2^21 = 2 MB away.

regards
Amit


		
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