> see, when interrupts are masked at PIC level, they are
> queued so that they can he forwarded to CPU when they
> unmasked, but I think only one interrupt per masked
> interrupt lines is queued, if that interrupt line is
> getting more than one interrupt, those will be lost
> (this is my understanding, I might be wrong, can some
> one on group confirm).
>
> If you are disableing the interrupts at CPU level ....
> those will be lost and will not be queued.
I think its the other way, if you mask interrupts, you are doing
it at the PIC/APIC/IO-APIC level, as Gaurav mailed, but once
they are masked, from what I know, the interrupts will be "ignored"
(read it as they never reach the CPU), so in essence they will
be "lost", intentionally though! (since its assumed that they programmer
knew what he is doing when he sent out the request to mask interrupts)
But, if you disable the interrupts (CLI etc...), then you are basically
asking the CPU not to accept them, but loosing or not loosing depends
on whether it is a "line based" or "edge triggered" interrupts, also
depends on whether the APIC/IO-APIC can buffer the interrupts and
transmit them to the CPU, if that is the case, then CPU will get
the piled up interrupt on STI.
Thanks,
Vinod
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