It said:
" Note that, in the actual code, the hierarchy is represented a little differently than has been portrayed above; each CPU has its own copy of every domain it belongs to. So our little system would actually contain eight sched_domain structures: one copy of the CPU-level domain and one copy of the top-level domain for every processor. Things are implemented this way for performance reasons: the scheduler must be very fast, which contraindicates sharing this fundamental data structure between processors. The structure is, in any case, almost entirely read-only after it has been set up, so it can be replicated without trouble."
but as I know, some fields of struct sched_domain are not read-only, they can be modified, such as
last_balance. If it need to maintain consistent state in each top-level sched_domain , it's better to share the structure . So top-level sched_domains's are inconsitent , my testing code confirmed this.
Inconsistent should be avoided , shouldn't it?
Please cast some lights on me, Thanks!
struct sched_domain {
/* These fields must be setup */
struct sched_domain *parent; /* top domain must be null terminated */
struct sched_group *groups; /* the balancing groups of the domain */
cpumask_t span; /* span of all CPUs in this domain */
unsigned long min_interval; /* Minimum balance interval ms */
unsigned long max_interval; /* Maximum balance interval ms */
unsigned int busy_factor; /* less balancing by factor if busy */
unsigned int imbalance_pct; /* No balance until over watermark */
unsigned long long cache_hot_time; /* Task considered cache hot (ns) */
unsigned int cache_nice_tries; /* Leave cache hot tasks for # tries */
unsigned int per_cpu_gain; /* CPU % gained by adding domain cpus */
int flags; /* See SD_* */ /* Runtime fields. */
unsigned long last_balance; /* init to jiffies. units in jiffies */
unsigned int balance_interval; /* initialise to 1. units in ms. */
unsigned int nr_balance_failed; /* initialise to 0 */
.........
}The following data from my testing code(two P4 xeon CPU),list all sched_domains and sched_groups
***************************
my_sched_domain
***************************
cpu id = 0 runqueue =0xc201ad60 sched_domain=0xc201a060
cpu id = 1 runqueue =0xc2022d60 sched_domain=0xc2022060
cpu id = 2 runqueue =0xc202ad60 sched_domain=0xc202a060
cpu id = 3 runqueue =0xc2032d60 sched_domain=0xc2032060
sched_domain c201a060 parent c201a0a0 groups c04a2340 span.bits[0] 3 min_interval 1 max_interval 2 busy_factor 8 imbalance_pct 110 cache_hot_time 0 cache_nice_tries 0 per_cpu_gain 15 flags 5f last_balance 25305297 balance_interval 2 nr_balance_failed 0
sched_domain c201a0a0 parent 00000000 groups c04a24c0 span.bits[0] 15 min_interval 1 max_interval 4 busy_factor 64 imbalance_pct 125 cache_hot_time 2500000 cache_nice_tries 1 per_cpu_gain 100 flags 37 last_balance 25305297 balance_interval 4 nr_balance_failed 1
sched_domain c2022060 parent c20220a0 groups c04a234c span.bits[0] 3 min_interval 1 max_interval 2 busy_factor 8 imbalance_pct 110 cache_hot_time 0 cache_nice_tries 0 per_cpu_gain 15 flags 5f last_balance 25305328 balance_interval 2 nr_balance_failed 0
sched_domain c20220a0 parent 00000000 groups c04a24c0 span.bits[0] 15 min_interval 1 max_interval 4 busy_factor 64 imbalance_pct 125 cache_hot_time 2500000 cache_nice_tries 1 per_cpu_gain 100 flags 37 last_balance 25305328 balance_interval 4 nr_balance_failed 3
sched_domain c202a060 parent c202a0a0 groups c04a2358 span.bits[0] 12 min_interval 1 max_interval 2 busy_factor 8 imbalance_pct 110 cache_hot_time 0 cache_nice_tries 0 per_cpu_gain 15 flags 5f last_balance 25305358 balance_interval 2 nr_balance_failed 0
sched_domain c202a0a0 parent 00000000 groups c04a24d8 span.bits[0] 15 min_interval 1 max_interval 4 busy_factor 64 imbalance_pct 125 cache_hot_time 2500000 cache_nice_tries 1 per_cpu_gain 100 flags 37 last_balance 25305359 balance_interval 4 nr_balance_failed 1
sched_domain c2032060 parent c20320a0 groups c04a2364 span.bits[0] 12 min_interval 1 max_interval 2 busy_factor 8 imbalance_pct 110 cache_hot_time 0 cache_nice_tries 0 per_cpu_gain 15 flags 5f last_balance 25305388 balance_interval 2 nr_balance_failed 0
sched_domain c20320a0 parent 00000000 groups c04a24d8 span.bits[0] 15 min_interval 1 max_interval 4 busy_factor 64 imbalance_pct 125 cache_hot_time 2500000 cache_nice_tries 1 per_cpu_gain 100 flags 37 last_balance 25305385 balance_interval 4 nr_balance_failed 0
group c04a2340
next c04a234c
cpumask.bits[0] 1
cpu_power 128group c04a234c
next c04a2340
cpumask.bits[0] 2
cpu_power 128group c04a24c0
next c04a24d8
cpumask.bits[0] 3
cpu_power 140group c04a24d8
next c04a24c0
cpumask.bits[0] 12
cpu_power 140group c04a2358
next c04a2364
cpumask.bits[0] 4
cpu_power 128group c04a2364
next c04a2358
cpumask.bits[0] 8
cpu_power 128
Best Regards
Bao Zhao
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