On Sat, 16 Oct 2004 08:08:26 +0300, Perfect Stranger <gilmour@xxxxxxxxxxx> wrote: > Selective enabling/disabling of IRQs is not the same as global > masking/unmasking of maskable interrupts. When the IF flag of the eflags > register is clear, each maskable interrupt issued by the PIC is temporarily > ignored by the CPU It might actually be helpful not to get too stuck in to how x86 does this. If you're out to understand how the kernel handles general concepts, such as interrupt generation, then it's not entirely useful to view everything in terms of particular Intel CPU registers :-). > so the disables interrupts are not sent at all while the masked interrupts > are sent but ignored by the CPU .. is this right ? Yes. They might be processed at a later stage, depending upon whether the line is unmasked and what is done to the PIC. > in case it's right i've jumped to this conclusion : disabled interrupts are > not lost cause they aren't send at all .. they are queued, but masked > interrupts are lost cause they are sent but ignored by the CPU > correct me please .. Disabled interrupts on the device aren't generated in the first place to be ignored. Masked interrupts in the PIC are queued for later handling when unmasking, disabled interrupts on the CPU result in the processor getting interrupted when subsequently enabled, if the PIC is still asserting the INT (or equilavent) pin(s). Jon. -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
