Processors like x86 will check its INTR pin after every instruction and will start executing the ISR if it finds it active. The procssor on finding an interrupt gate in the IDT will take an action equivalent to CLI, that is it disables its interrupt tracking functionality, this is because, it is the responsibility of the ISR to take appropriate action to clear the interrupt but this will require a few instrutions and as it is the feature of the processor to check for INTR active state after every instruction it will result in invoking the ISR again after the first instruction in the ISR itself. Linux commong interrupt handler will call STI to restore IF, but before that it will disable the interrupt at the interrupt controller level, this means that when your ISR executes, all the other interrupts except yours can interrupt the processor. >In other words, the IF flag makes the CPU ignore all maskable interrupts, >while masking a particular IRQ, it prevents the interrupt from reaching >the CPU. correct -----Original Message----- From: mbrennan@xxxxxxxx [mailto:mbrennan@xxxxxxxx] Sent: Friday, October 01, 2004 5:24 PM To: kernelnewbies@xxxxxxxxxxxx Subject: Understanding Interrupts Hello! I'm reading Understanding the Linux Kernel, and I'm trying to understand interrupts and exceptions properly. I wonder if I have understanded this correctly, this is how I think it works, and I would appreciate if someone could confirm that its right. So, is this correct? Linux's interrupts are interleaved, ie. they can be nested. That must mean that interrupts are enabled when handling interrupts. Now the thing that confuses me a little is that Linux uses interrupt gates, which clears the IF flag, and disables interrupts. But it seems like Linux sets the IF flag again before the actual handler. Is this to protect the code before the handler from being interrupted? If so, why is this neccesary? When interrupts are disabled by masking the maskable interrupts, does that mean that the CPU ignores the signal on the INTR pin. And when a IRQ is masked on the PIC, does that mean that the PIC doesn't send any interrupt to the CPU when that IRQ is raised? In other words, the IF flag makes the CPU ignore all maskable interrupts, while masking a particular IRQ, it prevents the interrupt from reaching the CPU. When executing an interrupt handler, maskable interrupts are enabled but the IRQ of the interrupt is masked out. Other interrupts may interrupt the execution, but not the same as the one currently executed? Thank you! /Michael -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/ -- Kernelnewbies: Help each other learn about the Linux kernel. Archive: http://mail.nl.linux.org/kernelnewbies/ FAQ: http://kernelnewbies.org/faq/
