pcsp_beep(int count, int cycles)
{
/* enable counter 2 */
outb_p(inb_p(0x61)|3, 0x61);
/* set command for counter 2, 2 byte write */
outb_p(0xB6, 0x43);
/* select desired HZ */
outb_p(count & 0xff, 0x42);
outb((count >> 8) & 0xff, 0x42);
while (cycles--);
/* disable counter 2 */
outb(inb_p(0x61)&0xFC, 0x
this is patch of patch of PCSP it's just produces beep
of count HZ,
sorry but a simple questions is why this while
(cycles --) used
2. it used timer 0 as rate generator and timer 2 as in
one shot,
instead we used timer0 in interrupt mode and allow it
to give irq0 and in that ISR count is given to timer2
accroding to samples,
then it's there in book linux kernel programming that
if it is so then it will make things complex as at the
same time normal interrupt rate which kernel used
for various purpose like scheduling has to do from
our handler to maintain that interrupt rate also(i
don't know but i think jiffies also update by this
tick,sorry if wrong),
can anybody explains that how then the code of that
small (ISR )handler?which manage both of above and
exits
thanks
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