Re: page coloring implementation

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>>>>> "tbisson" == tbisson  <tbisson@soe.ucsc.edu> writes:

tbisson> Yeah, several sources I've seen give that equation.

Ok.

tbisson> Question: cache stores "physical page addresses" (on P4's), right?
tbisson> I have a 512K cache w/64B lines and is 8-way.

  Nope, the cache (the one that is 512K) stores the memory content,
not memory addresses.  The TLB stores addresses.

tbisson> If so, then cache_size/page_size = number of colors for a
tbisson> direct mapped.  For example 4096K cache size and 4K pages,
tbisson> then there are 1024 colors or physical_page_address_indexes
tbisson> that won't conflict. Thus, if we have a process we want to
tbisson> improve performance with, we assign it physical pages
tbisson> contigouslly from

tbisson> "phy_page_num mod num_colors =0" to "phy_page_num mod
tbisson> num_colors = num_colors -1"

tbisson> so that it uses all the cache.

  Right.  With set-associative caches page coloring helps allocating
pages whose lines cache to different sets.

 Let for concreteness use 32-bit addresses, 512K, 8-way set-associative
cache, 64-byte cache line size.

  The address is split like <tag:16 set:10 byte:6>.  The ``set'' field
selects one of 1024 == 512K / (8 * 64) sets and the cache line goes to
either of the 8 ways of the set.  The page allocation affects the
upper 4 bits of the ``set'' field.  If two pages has these 4 bit
different (== having different color), the lines in them cache to
different sets, thus do not conflict.  

tbisson> If the L2 cache stores "physical page addresses", what use
tbisson> would the cache be without a TLB? It seems like they are
tbisson> dependent upon each other for performacne?

  Nope, they are independent.  The cache caches ordinary memory, the
TLBs cache address translation results.

Tim> num_colors = cache_size/(associativity*page_size).

>> Page coloring is made to improve the utilization of the TLBs.
 
  Actually, that statement of mine is NOT true.  Even more with
fully-associative TLBs.

~velco

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