OK, that is what I understood to be true. And to be honest, I should have realized on my own that your description did fit the real mode case.
Regards,
Don
sridhar vaidyanathan writes:
Quoting Don Dade <ddade@digitalstatecraft.com>:
Please correct me if I am wrong, but are these statements accurate?
"EIP contains the linear address of the next instruction within the code segment to be executed."
"This address can be thought of as an index in to the 4GB linear (virtual) address space of the process."
I thought that all the general registers contained *virtual* addresses, which are transformed by the memory management hardware into linear addresses, which are further transformed by the paging hardware into physical addresses, in fact passing through the lower 12 bits. The above statements seem to imply that linear and virtual are the same thing, which I
thought was absolutely not the case.
Maybe I don't understand x86 as well as I think I do :)
Don
"EIP contains the linear address of the next instruction within the codesegment to be executed."This statement was from the intel arch manual.I think the confusion came from the fact that CS:IP combination is referred to as logical address under protected mode memory model.In the section that I picked the statement from there is no mention of protected mode as such.So they might've have meant just real mode. Sorry about not mentioning it.
Basically in x86 terminology under protected mode memory model , there are 3 kinds of addresses : logical(what you have refered to as virtual in your post ie CS:EIP),linear(after segmentation h/w) and physical(after paging).
"This address can be thought of as an index in to the 4GB linear (virtual) address space of the process."When I interchanged the terms virtual and linear i meant address spaces, which is virtual as well as linear (0 - 2^32 -1).
hope there is not confusion now :-)
sridhar
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