On Tue, 12 Nov 2002 Seth Arnold wrote :
>On Tue, Nov 12, 2002 at 05:03:00AM -0000, Nishant Sharma wrote:
> > can somebody clear me on this.. what exactly is a memory
>barrier
> > ?? AFAIK .. it is used to commit writes to _memory_
>(cacheable)
> > before doing a crucial read op.
>Reads and writes both. (Writes can matter for devices.)
So in effect it is required for ordering of the I/O
and memory refrences across crucial pieces of code (and this is
where _prefething_ etc comes into play)
> > secondly in the IA32 and PPC processor how is it
>implemented
> > ???? i saw the generated assembly of a simple
> > main(){
> >
> > /* Barrier */
> > __asm__ __volatile__ ("" : : :"memory"); // i think i dont
>need
> > the __volatile__ here ..
> > }
> >
> > and the assembly source didnt show me nething in either of
>the
> > cases (PPC / IA32).
>
>The "memory" bit tells gcc that the inline assembly may have
>modified the
>memory, and the volatile tells gcc that it has to commit writes
>to memory
>-- flushing the cpu's cache, etc. The assembly itself doesn't do
>it --
>the inline assembly statement is being used only for its side
>effects.
>
I dont xactly get u here ;). Firstly ive seen in the Linux code
that i dont need to place a __volatile__ for the barrier
implementation code and it is being used because of a gcc bug, so
it is not supposed to be there ?? is it ??
Secondly, in IA32 a locked instruction is guarantees u a total
ordering around that instruction (and CPUID inst too guarantees
that). So when i need a barrier across two insts ... what code
will the barrier() expand to ..
sth like --
write A
mb() // barrier
read B
Sorry for bothering ... i might be totally wrong here ..:)
Nishant
>--
>http://www.wirex.com/
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